格雷码和二进制的相互转换vhdl程序剖析.docx
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格雷码和二进制的相互转换vhdl程序剖析.docx
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格雷码和二进制的相互转换vhdl程序剖析
1.B2G_converter
1)ScreenshotofiSimsimulationresults:
note:
fromthebeginningpointat1,000ns,input(i5binary)changeseveryother50ns
a)i5binaryinputfrom0to6
i5binary
o5graycode
Delayofoutput(ns)
00000
00000
6.691
00001
00001
6.516
00010
00011
6.517
00011
00010
6.516
00100
00110
6.580
00101
00111
6.516
00110
00101
6.517
b)i5binaryinputfrom7to13
i5binary
o5graycode
Delayofoutput(ns)
00111
00100
6.516
01000
01100
6.197
01001
01101
6.516
01010
01111
6.517
01011
01110
6.516
01100
01010
6.580
01101
01011
6.516
c)i5binaryinputfrom14to20
i5binary
o5graycode
Delayofoutput(ns)
01110
01001
6.517
01111
01000
6.516
10000
11000
5.210
10001
11001
6.516
10010
11011
6.517
10011
11010
6.516
10100
11110
6.580
d)i5binaryinputfrom21to27
i5binary
o5graycode
Delayofoutput(ns)
10101
11111
6.516
10110
11101
6.517
10111
11100
6.516
11000
10100
6.197
11001
10101
6.516
11010
10111
6.517
11011
10110
6.516
e)i5binaryinputfrom28to31
i5binary
o5graycode
Delayofoutput(ns)
11100
10010
6.580
11101
10011
6.516
11110
10001
6.517
11111
10000
6.516
2)VHDLforBinary-to-Gray-Codeconverter:
----------------------------------------------------------------------------------
--Company:
--Engineer:
--
--CreateDate:
13:
02:
3709/15/2015
--DesignName:
--ModuleName:
b2g_converter-Behavioral
--ProjectName:
--TargetDevices:
--Toolversions:
--Description:
--
--Dependencies:
--
--Revision:
--Revision0.01-FileCreated
--AdditionalComments:
--
----------------------------------------------------------------------------------
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;
--Uncommentthefollowinglibrarydeclarationifinstantiating
--anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;
entityb2g_converteris
Port(i5Binary:
inSTD_LOGIC_VECTOR(4downto0);
o5GrayCode:
outSTD_LOGIC_VECTOR(4downto0));
endb2g_converter;
architectureBehavioralofb2g_converteris
signalgbuffer:
std_logic_vector(4downto0);
begin
o5GrayCode<=gbuffer;
gbuffer(4)<=i5Binary(4);
label1:
foriin3downto0generate
gbuffer(i)<=i5Binary(i+1)xori5Binary(i);
endgenerate;
endBehavioral;
2.G2B_converter
1)Gray-code-to-Binaryconversion
Fromthecombinationallogicdescribedforgray-code-to-binaryconversion,weobtain:
Inn-bitconversion,forbitsinposition0ton-2:
g(i)
b(i+1)
b(i)
0
1
1
0
0
0
1
0
1
1
1
0
Thus,foran-bitgraycodenumberg,g=g(n-1)g(n-2)…g
(2)g
(1)g(0),thecorrespondingn-bitbinarynumberb,b=b(n-1)b(n-2)…b
(2)b
(1)b(0)iscomputedusingthefollowingdescription:
b(n-1)=g(n-1)fortheMSB,and
b(i)=g(i)
b(i+1)forbitsinposition0ton-2
2)ScreenshotofiSimsimulationresults:
note:
fromthebeginningpointat1,000ns,input(i5graycode)changeseveryother50ns
a)i5graycodeinputfrom0to6
i5graycode
o5binary
Delayofoutput(ns)
00000
00000
6.755
00001
00001
6.755
00010
00011
6.517
00011
00010
6.755
00100
00111
6.755
00101
00110
6.755
00110
00100
6.517
b)i5graycodeinputfrom7to13
i5graycode
o5binary
Delayofoutput(ns)
00111
00101
6.755
01000
01111
6.755
01001
01110
6.755
01010
01100
6.517
01011
01101
6.755
01100
01000
6.755
01101
01001
6.755
c)i5graycodeinputfrom14to20
i5graycode
o5binary
Delayofoutput(ns)
01110
01011
6.517
01111
01010
6.755
10000
11111
6.747
10001
11110
6.755
10010
11100
6.517
10011
11101
6.755
10100
11000
6.755
d)i5graycodeinputfrom21to27
i5graycode
o5binary
Delayofoutput(ns)
10101
11001
6.755
10110
11011
6.517
10111
11010
6.755
11000
10000
6.755
11001
10001
6.755
11010
10011
6.517
11011
10010
6.755
e)i5graycodeinputfrom28to31
i5graycode
o5binary
Delayofoutput(ns)
11100
10111
6.755
11101
10110
6.755
11110
10100
6.517
11111
10101
6.755
3)VHDLforGray-Code-to-Binaryconverter:
----------------------------------------------------------------------------------
--Company:
--Engineer:
--
--CreateDate:
15:
20:
0309/15/2015
--DesignName:
--ModuleName:
g2b_converter-Behavioral
--ProjectName:
--TargetDevices:
--Toolversions:
--Description:
--
--Dependencies:
--
--Revision:
--Revision0.01-FileCreated
--AdditionalComments:
--
----------------------------------------------------------------------------------
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;
--Uncommentthefollowinglibrarydeclarationifinstantiating
--anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;
entityg2b_converteris
Port(i5GrayCode:
inSTD_LOGIC_VECTOR(4downto0);
o5Binary:
outSTD_LOGIC_VECTOR(4downto0));
endg2b_converter;
architectureBehavioralofg2b_converteris
signalbbuffer:
std_logic_vector(4downto0);
begin
o5Binary<=bbuffer;
bbuffer(4)<=i5GrayCode(4);
label1:
foriin3downto0generate
bbuffer(i)<=bbuffer(i+1)xori5GrayCode(i);
endgenerate;
endBehavioral;
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