程序分析.docx
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程序分析.docx
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程序分析
1.1. 分析下面程序,说出该程序的功能。
Entitytestis
generic(setup_time:
time:
=5ns);
port(D:
instd_logic;
Q:
outstd_logic;
clk:
instd_logic);
endtest;
architecturetestoftestis
begin
process(clk)
begin
ifclk=‘1’andclk’eventthen
assert(D’last_event>setup_time)
report“setupviolation”
severityerror;
endif;
endtest;
2.2. 分析下面程序,说出该程序的功能。
libraryIEEE;
useIEEE.STD_LOGIC_1164.all;
entitys_machineis
port(
clk:
inSTD_LOGIC;
rst:
inSTD_LOGIC;
din:
inSTD_LOGIC;
comb_output:
outSTD_LOGIC
);
ends_machine;
architectures_machineofs_machineis
typestatesis(st0,st1,st2,st3);
signalcur_state,next_state:
states;
begin
process(clk,rst)
begin
ifrst='1'then
cur_state<=st0;
elsifclk'eventandclk='1'then
cur_state<=next_state;
endif;
endprocess;
process(cur_state,next_state)
begin
casecur_stateis
whenst0=>comb_output<=‘0’;
ifdin=‘1’then
next_state<=st1;
else
next_state<=st0;
endif;
whenst1=>comb_output<=‘0’;
ifdin=‘1’then
next_state<=st2;
else
next_state<=st0;
endif;
whenst2=>
ifdin=‘1’then
next_state<=st3;
comb_output<=‘1’;
elsenext_state<=st0;
comb_output<=‘0’;
endif;
whenst3=>ifstate_input=‘1’then
next_state<=st3;
comb_output<=‘1’;
elsenext_state<=st0;
comb_output<=‘0’;
endif;
endcase;
endprocess;
ends_machine;
3.3. 分析下面程序,指出该程序的功能。
process(a,dr,en)
begin
ifen='0'anddr='1'then
bout<=a;
else
bout<="ZZZZZZZZ";
endif;
b<=bout;
endprocess;
process(a,dr,en)
begin
ifen='0'anddr='0'then
aout<=b;
else
aout<="ZZZZZZZZ";
endif;
a<=aout;
endprocess;
4.4. 分析下面程序,指出电路功能。
libraryIEEE;
useIEEE.STD_LOGIC_1164.all;
entityshiftis
port(clk:
inSTD_LOGIC;
a:
inSTD_LOGIC;
b:
outSTD_LOGIC);
endshift;
architectureshiftofshiftis
begin
componentdff
port(d,clk:
instd_logic;
q:
outstd_logic);
endcomponent;
signalz:
std_logic_vector(0to4);
begin
z(0)<=a;
g1:
foriin0to3generate
dffx:
dffportmap(z(i),clk,z(i+1));
endgenerate;
b<=z(4);
endshift;
5.分析下面程序,所明该程序的功能。
libraryIEEE;
useIEEE.STD_LOGIC_1164.all;
entitychkis
port(
din:
inSTD_LOGIC;
clk,clr:
inSTD_LOGIC;
d:
inSTD_LOGIC_VECTOR(7downto0);
check_out:
outSTD_LOGIC
);
endchk;
architecturechkofchkis
signalq:
integerrange0to8;
begin
process(clk,clr)
begin
ifclr='1'thenq<=0;
elsifclk'eventandclk='1'then
caseqis
when0=>ifdin=d(7)thenq<=1;elseq<=0;endif;
when1=>ifdin=d(6)thenq<=2;elseq<=0;endif;
when2=>ifdin=d(5)thenq<=3;elseq<=0;endif;
when3=>ifdin=d(4)thenq<=4;elseq<=0;endif;
when4=>ifdin=d(3)thenq<=5;elseq<=0;endif;
when5=>ifdin=d
(2)thenq<=6;elseq<=0;endif;
when6=>ifdin=d
(1)thenq<=7;elseq<=0;endif;
when7=>ifdin=d(0)thenq<=8;elseq<=0;endif;
whenothers=>q<=0;
endcase;
endif;
endprocess;
process(q)
begin
ifq=8thencheck_out<='1';
elsecheck_out<='0';
endif;
endprocess;
endchk;
6.分析下面程序,所明该程序的功能。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitypulseis
port(clk,rst:
instd_logic;
d:
instd_logic_vector(7downto0);
fout:
outstd_logic);
endpulse;
architectureoneofpulseis
signalfull:
std_logic;
signalcnt8:
std_logic_vector(7downto0);
signalfout_tmp:
std_logic;
begin
p_reg:
process(clk)
begin
ifrst='1'then
cnt8<=(others=>'1');
full<='0';
elsifclk'eventandclk='1'then
ifcnt8="11111111"then
cnt8<=d;--当cnt8计数计满时,输入数据d被预置给计数器cnt8
full<='1';--同时使溢出标志信号full输出为高电平
elsecnt8<=cnt8+1;--否则继续作加1计数
full<='0';--且输出溢出标志信号full为低电平
endif;
endif;
endprocessp_reg;
p_div:
process(full)
begin
ifrst='1'then
fout_tmp<='0';
elsiffull'eventandfull='1'then
fout_tmp<=notfout_tmp;--如果full为高电平,d触发器输出取反
endif;
endprocessp_div;
fout<=fout_tmp;
endone;
7.分析下面程序,所明该程序的功能。
libraryIEEE;
useIEEE.STD_LOGIC_1164.all;
entitynand2is
port(
a:
inSTD_LOGIC;
b:
inSTD_LOGIC;
y:
outSTD_LOGIC
);
endnand2;
architecturenand2ofnand2is
begin
process(a,b)
variablecomb:
std_logic_vector(1downto0);
comb:
=a&b;
casecombis
when"00"=>y<='1';
when"01"=>y<='1';
when“10"=>y<='1';
when“11"=>y<='0';
whenothers=>y<='Z';
endcase;
endprocess;
endnand2;
8.分析下面程序,说明其功能。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux4IS
PORT(input:
INSTD_LOGIC_VECTOR(3DOWNTO0);
sel:
INSTD_LOGIC_VECTOR(1DOWNTO0);
y:
outSTD_LOGIC);
ENDmux4;
ARCHITECTURErtlOFmux4IS
BEGIN
PROCESS(input,sel)
BEGIN
IFsel=”00”THEN
y<=input(0);
ELSIFsel=”01”THEN
y<=input
(1);
ELSIFsel=”10”THEN
y<=input
(2);
ELSE
y<=input(3);
ENDIF;
ENDPROCESS;
ENDrtl;
9.分析下面程序,说明其功能。
libraryIEEE;
useIEEE.STD_LOGIC_1164.all;
entitytestis
port(
a:
inSTD_LOGIC;
b:
inSTD_LOGIC;
y:
outSTD_LOGIC
);
endnand2;
architecturetestoftestis
begin
process(a,b)
variablecomb:
std_logic_vector(1downto0);
comb:
=a&b;
casecombis
when"00"=>y<='0';
when"01"=>y<='1';
when“10"=>y<='1';
when“11"=>y<='0';
whenothers=>y<='Z';
endcase;
endprocess;
endtest;
10.分析下面程序,说明其功能。
libraryIEEE;
useIEEE.STD_LOGIC_1164.all;
entityhalf_adderis
port(
a:
inSTD_LOGIC;
b:
inSTD_LOGIC;
s:
outSTD_LOGIC;
co:
outSTD_LOGIC
);
endhalf_adder;
architecturehalf_adderofhalf_adderis
signalc,d:
std_logic;
begin
c<=aorb;
d<=anandb;
co<=notd;
s<=candd;
endhalf_adder;
libraryIEEE;
useIEEE.STD_LOGIC_1164.all;
entitytestis
port(
a,b,cin:
inSTD_LOGIC;
co,s:
outSTD_LOGIC);
endtest;
architecturetestoftestis
componenthalf_adder
port(
a,b:
inSTD_LOGIC;
s,co:
outSTD_LOGIC);
endcomponent;
signalu0_co,u0_s,u1_co:
std_logic;
begin
u0:
half_adderportmap(a,b,u0_s,u0_co);
u1:
half_adderportmap(u0_s,b,cin,s,u1_co);
co<=u0_cooru1_co;
endtest;
11.分析下面的VHDL源程序,说明设计电路的功能。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitylx3_1is
port(s2,s1,s0:
instd_logic;
d3,d2,d1,d0:
instd_logic;
d7,d6,d5,d4:
instd_logic;
y:
outstd_logic);
endlx3_1;
architectureoneoflx3_1is
signals:
std_logic_vector(2downto0);
begin
s<=s2&s1&s0;
y<=d0whens="000"else
d1whens="001"else
d2whens="010"else
d3whens="011"else
d4whens="100"else
d5whens="101"else
d6whens="110"else
d7;
endone;
12.分析下面的VHDL源程序,说明设计电路的功能。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitylx3_2is
port(a:
instd_logic_vector(3downto0);
b:
instd_logic_vector(3downto0);
gt,lt,eq:
outstd_logic);
endlx3_2;
architectureoneoflx3_2is
begin
process(a,b)
begin
gt<='0';
lt<='0';
eq<='0';
ifa>bthengt<='1';
elsifa elseeq<='1'; endif; endprocess; endone; 13.分析下面的VHDL源程序,说明设计电路的功能。 libraryieee; useieee.std_logic_1164.all; entitylx3_3is port(abin: instd_logic_vector(7downto0); din: instd_logic_vector(7downto0); dout: outstd_logic_vector(7downto0)); endlx3_3; architectureoneoflx3_3is begin process(abin,din) begin foriin0to7loop dout(i)<=din(i)andabin(i); endloop; endprocess; endone; 14.分析下面的VHDL源程序,说明设计电路的功能。 libraryieee; useieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entitylx3_4is port(clk: instd_logic; j,k: instd_logic; q,qn: outstd_logic); endlx3_4; architecturestrucoflx3_4is signalq_temp: std_logic: ='0'; signaljk: std_logic_vector(1downto0); begin jk<=j&k; process(clk,j,k) begin ifclk'eventandclk='0'then casejkis when"00"=>q_temp<=q_temp; when"01"=>q_temp<='0'; when"10"=>q_temp<='1'; when"11"=>q_temp<=notq_temp; whenothers=>q_temp<='X'; endcase; endif; q<=q_temp; qn<=notq_temp; endprocess; endstruc; 15.分析下面VHDL源程序,分别给出tim1~tim9的值。 Architecturetimeoftimeis Typetimis(sec,min,hous,day,month,year); Subtypereverse_timis Timrangemonthdowntomin; Signaltim1,tim2,tim3,tim4,tim5,tim6,tim7,tim8: time; begin tim1<=tim’left; Tim2<=tim’right; Tim3<=tim’high; Tim4<=tim’low; Tim5<=reverse_tim’left; Tim6<=reverse_tim’right; Tim7<=reverse_tim’high; tim8<=reverse_tim’low; tim9<=tim’length; Endtime; 16.分析下面程序,说出该程序的功能。 LIBRARYIEEE; USEIEEE.std_logic_1164.all; ENTITYselsIS PORT(d,clk: INSTD_LOGIC; q,nq: OUTSTD_LOGIC); ENDsels; IFclk=‘1’ANDclk’EVENTTHEN q<=d; Nq<=NOTq; ENDIF; 17.分析下面程序,说出该程序的功能。 libraryIEEE; useIEEE.STD_LOGIC_1164.all; entitys_machineis port( clk: inSTD_LOGIC; rst: inSTD_LOGIC; din: inSTD_LOGIC; comb_output: outSTD_LOGIC ); ends_machine; architectures_machineofs_machineis typestatesis(st0,st1,st2,st3); signalcur_state,next_state: states; begin process(clk,rst) begin ifrst='1'then cur_state<=st0; elsifclk'eventandclk='1'then cur_state<=next_state; endif; endprocess; process(cur_state,next_state) begin casecur_stateis whenst0=>comb_output<=‘0’; ifdin=‘1’then next_state<=st1; else next_state<=st0; endif; whenst1=>comb_output<=‘0’; ifdin=‘1’then next_state<=st2; else next_state<=st0; endif; whenst2=> ifdin=‘1’then next_state<=st3; comb_output<=‘1’; elsenext_state<=st0; comb_output<=‘0’; endif; whenst3=>ifstate_input=‘1’then next_state<=st3; comb_output<=‘1’; elsenext_state<=st0; comb_output<=‘0’; endif; endcase; endprocess; ends_machine; 18.分析下面程序,指出该程序的功能。 L
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