CPU实验报告pdf.docx
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CPU实验报告pdf.docx
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CPU实验报告pdf
ComputerOrganizationandArchitecture
CourseDesign
MicroprogrammedCPU
Design
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CPUDesignReport
Purpose
ThepurposeofthisprojectistodesignasimpleCPU(CentralProcessing
Unit).ThisCPUhasbasicinstructionset,andwewillutilizeits
instructionsettogenerateaverysimpleprogramtoverifyits
performance.Forsimplicity,wewillonlyconsidertherelationship
amongtheCPU,registers,memoryandinstructionset.Thatistosaywe
onlyneedconsiderthefollowingitems:
Read/WriteRegisters,
Read/WriteMemoryandExecutetheinstructions.
AtleastfourpartsconstituteasimpleCPU:
thecontrolunit,theinternal
registers,theALUandinstructionset,whicharethemainaspectsofour
projectdesignandwillbestudied.
InstructionSet
Single-addressinstructionformatisusedinoursimpleCPUdesign.The
instructionwordcontainstwosections:
theoperationcode(opcode),
whichdefinesthefunctionofinstructions(addition,subtraction,logic
operations,etc.);theaddresspart,inmostinstructions,theaddresspart
containsthememorylocationofthedatumtobeoperated,wecalledit
directaddressing.Insomeinstructions,theaddresspartistheoperand,
whichiscalledimmediateaddressing.
Forsimplicity,thesizeofmemoryis256×16inthecomputer.The
instructionwordhas16bits.Theopcodeparthas8bitsandaddresspart
2
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has8bits.TheinstructionwordformatcanbeexpressedinFigure4
Figure4theinstructionformat
TheopcodeoftherelevantinstructionsarelistedinTable1.
InTable1,thenotation[x]representsthecontentsofthelocationxinthe
memory.Forexample,theinstructionword00000011101110012
(03B916)meansthattheCPUaddswordatlocationB916inmemory
intotheaccumulator(ACC);theinstructionword00000101000001112
(050716)meansifthesignbitoftheACC(ACC[15])is0,theCPUwill
usetheaddresspartoftheinstructionastheaddressofnextinstruction,
ifthesignbitis1,theCPUwillincreasetheprogramcounter(PC)and
useitscontentastheaddressofthenextinstruction.
3
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CPUDesignReport
QUESTION
1、Calculatethesumofallintegersfrom1to100.
1.programmingwithClanguage:
sum=0;
temp=100;
loop:
sum=sum+temp;
temp=temp-1;
iftemp>=0gotoloop;
4
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CPUDesignReport
end
2.Assumeinthememory:
sumisstoredatlocationA4,
tempisstoredatlocationA3,
thecontentsoflocationA0is0,
thecontentsoflocationA1is1,
thecontentsoflocationA2is10010=6416.
WecantranslatetheaboveClanguageprogramwiththeinstructions
listedinTable1intotheinstructionprogramasshowninTable2.
Table2Exampleofaprogramtosumfrom1to100
ProgramwithC
Programwith
instructions
ContentsofMemory(RAM)in
HEX
Address
Contents
LOADA0
STOREA4
LOADA2
STOREA3
LOOP:
LOADA4
00
02A0
sum=0;
01
02
03
01A4
02A2
01A3
temp=100;
04(soLOOP=04)02A4
loop:
sum=sum+temp;ADDA3
05
06
07
08
09
03A3
01A4
02A3
04A1
01A3
STOREA4
LOADA3
SUBA1
STOREA3
temp=temp-1;
5
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CPUDesignReport
iftemp>=0gotoloop;
end
JMPGEZLOOP
0A
0B
0C
……
A0
A1
A2
A3
A4
A5
……
0504
HALT
HALT
……
0000
0001
0064
……
2、Youmayprogramtomultiply6by5,-6by5and-6by-5usingMPY
instruction,andthenchecktheresults.
InternalRegistersandMemory
MAR(MemoryAddressRegister)
MARcontainsthememorylocationofthewordtobereadfromthe
memoryorwrittenintothememory.Here,READoperationisdenotedas
theCPUreadsfrommemory,andWRITEoperationisdenotedasthe
CPUwritestomemory.Inourdesign,MARhas8bitstoaccessoneof
256addressesofthememory.
MBR(MemoryBufferRegister)
6
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MBRcontainsthevaluetobestoredinmemoryorthelastvalueread
frommemory.MBRisconnectedtotheaddresslinesofthesystembus.
Inourdesign,MBRhas16bits.
PC(ProgramCounter)
PCkeepstrackoftheinstructionstobeusedintheprogram.Inour
design,PChas8bits.
IR(InstructionRegister)
IRcontainstheopcodepartofaninstruction.Inourdesign,IRhas8bits.
BR(BufferRegister)
BRisusedasaninputofALU,itholdsotheroperandforALU.Inour
design,BRhas16bits.
ACC(Accumulator)
ACCholdsoneoperandforALU,andgenerallyACCholdsthe
calculationresultofALU.Inourdesign,ACChas16bits.
MR(MultiplierRegister)
MRisusedforimplementingtheMPYinstruction,holdingthemultiplier
atthebeginningoftheinstruction.Whentheinstructionisexecuted,it
holdspartoftheproduct.
DR(DivisionRegister)
DRisusedforimplementingtheDIVinstruction,youcandefineit
accordingtoyourdivisionalgorithm.
LPM_RAM_DQ
7
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CPUDesignReport
LPM_RAM_DQisaRAMwithseparateinputandoutputports,itworks
asmemory,anditssizeis256×16.Althoughit’snotaninternalregister
ofCPU,weneedittosimulateandtesttheperformanceofCPU.
Alltheregistersarepositive-edge-triggered.
Alltheresetsignalsfortheregistersaresynchronizedtotheclocksignal.
ALU
ALU(ArithmeticLogicUnit)isacalculationunitwhichaccomplishes
basicarithmeticandlogicoperations.
MicroprogrammedControlUnit
WehavelearnttheknowledgeofMicroprogrammedcontrolunit.Here,
weonlyreviewsometermsandbasicstructures.
IntheMicroprogrammedcontrol,themicroprogramconsistsofsome
microinstructionsandthemicroprogramisstoredincontrolmemorythat
generatesallthecontrolsignalsrequiredtoexecutetheinstructionset
correctly.Themicroinstructioncontainssomemicro-operationswhich
areexecutedatthesametime.
8
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Figure5showsthekeyelementsofsuchanimplementation.Thesetof
microinstructionsisstoredinthecontrolmemory.Thecontroladdress
registercontainstheaddressofthenextmicroinstructionstoberead.
Whenamicroinstructionisreadfromthecontrolmemory,itis
transferredtoacontrolbufferregister.Theregisterconnectstothe
controllinesemanatingfromthecontrolunit.Thus,readinga
microinstructionfromthecontrolmemoryisthesameasexecutingthat
microinstruction.Thethirdelementshowninthefigureisasequencing
unitthatloadsthecontroladdressregisterandissuesareadcommand.
9
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CPUDesignReport
CPUDesign
Figure6indicatesasimpleCPUarchitectureanditsuseofavarietyof
internaldatapathsandcontrolsignals.OurCPUdesignshouldbebased
onthisarchitecture.
YoushoulddeterminethecontrolsignalsaccordingtotheCPU
architectureandyourdesign.Anexampleisgivenbelowtoshowthe
procedure,thisexampledescribesthecontrolunitdesignfortheLOAD
instruction.
First,weneeddeterminethecontrolflowchartoftheLOADinstruction.
Thenweneedtodeterminetherelevantcontrolsignalswhicharegiven
below.
10
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Themeaningofeverybitofthecontrolmemory(ROM)
C1
CAR←CAR+1
CAR←***
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
CAR←0
MBR←memory
IR←MBR[15…8]
MAR←MBR[7…0]
PC←PC+1
BR←MBR
ACC←0
ACC←ALU
MAR←PC
MBR←ACC
memory←MBR
ALU←ACC+BR
ALU←ACC-BR
ALU←ACC*BR
ALU←(ACC)and(BR)
ALU←(ACC)or(BR)
ALU←not(ACC)
ALU←shift(ACC)toleft1bits
ALU←shift(ACC)toright1bits
11
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CPUDesignReport
C22
C23
PC←MBR[7…0]
PC←0
microoperations
32109876543210987654321
00000000000000000001001C4,C1
00000000000000000010001C5,C1
00000000000000000000010C2
00000000000000001100001C6,C7,C1
00000000000100000000001C12,C1
00000000001000000000001C13,C1
00000000000010000000100C11,C3
00000000000000000001001C4,C1
00000000000000000010001C5,C1
00000000000000000000010C2
00000000000000001100001C6,C7,C1
00000000000000000001001C4,C1
00000000000000110000001C8,C9,C1
00000000010000000000001C14,C1
00000000000001000000001C10,C1
00000000000010000000100C11,C3
00000000000000000001001C4,C1
00000000000000000010001C5,C1
00000000000000000000010C2
00000000000000001100001C6,C7,C1
00000000000000000001001C4,C1
00000000000000010000001C8,C1
00000000010000000000001C14,C1
00000000000001000000001C10,C1
00000000000010000000100C11,C3
00000000000000000001001C4,C1
00000000000000000010001C5,C1
00000000000000000000010C2
00000000000000001100001C6,C7,C1
00000000000000000001001C4,C1
00000000000000010000001C8,C1
00000000100000000000001C15,C1
STORE
MBR←memory,CAR←CAR+1
IR←MBR[15…8],CAR←CAR+1
CAR←**(**取决于opcode)
MAR←MBR[7…0],PC←PC+1,CAR←CAR+1
MBR←ACC,CAR←CAR+1
memory←MBR,CAR←CAR+1
MAR←PC,CAR←0
LOAD
MBR←memory,CAR←CAR+1
IR←MBR[15…8],CAR←CAR+1
CAR←**(**取决于opcode)
MAR←MBR[7…0],PC←PC+1,CAR←CAR+1
MBR←memory,CAR←CAR+1
BR←MBR,ACC←0,CAR←CAR+1
ALU←ACC+BR,CAR←CAR+1
ACC←ALU,CAR←CAR+1
MAR←PC,CAR←0
ADD
MBR←memory,CAR←CAR+1
IR←MBR[15…8],CAR←CAR+1
CAR←**(**取决于opcode)
MAR←MBR[7…0],PC←PC+1,CAR←CAR+1
MBR←memory,CAR←CAR+1
BR←MBR,CAR←CAR+1
ALU←ACC+BR
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