EDA实验程序大集合.docx
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EDA实验程序大集合.docx
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EDA实验程序大集合
用CASE语句描述4选1多路选择器。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYMUX41IS
PORT(S1,S2:
INSTD_LOGIC;
A,B,C,D:
INSTD_LOGIC;
Z:
OUTSTD_LOGIC);
ENDENTITYMUX41;
ARCHITECTUREARTOFMUX41IS
SIGNALS:
STD_LOGIC_VECTOR(1DOWNTO0);
BEGIN
S<=S1&S2;
PROCESS(S1,S2,A,B,C,D)
BEGIN
CASESIS
WHEN"00"=>Z<=A;
WHEN"01"=>Z<=B;
WHEN"10"=>Z<=C;
WHEN"11"=>Z<=D;
WHENOTHERS=>Z<='X';
ENDCASE;
ENDPROCESS;
ENDART;
ENDART1;
三八译码器方法1:
使用IF语句
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYENCODERIS
PORT(IN1:
INSTD_LOGIC_VECTOR(7DOWNTO0);
OUT1:
OUTSTD_LOGIC_VECTOR(2DOWNTO0));
ENDENCODER;
ARCHITECTUREART3OFENCODERIS
BEGIN
PROCESS(INT1)
BEGIN
IFIN1(7)=‘1’THENOUT1<="111";
ELSIFIN1(6)=‘1’THENOUT1<="110";
ELSIFIN1(5)=‘1’THENOUT1<="101";
ELSIFIN1(4)=‘1’THENOUT1<="100";
ELSIFIN1(3)=‘1’THENOUT1<="011";
ELSIFIN1
(2)=‘1’THENOUT1<="010";
ELSIFIN1
(1)=‘1’THENOUT1<="001";
ELSIFIN1(0)=‘1’THENOUT1<="000";
ELSEOUT1<="XXX";
ENDIF;
ENDPROCESS;
ENDART3;
【例4.23】T触发器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYTCFQIS
PORT(T,CLK:
INSTD_LOGIC;
Q:
BUFFERSTD_LOGIC);
ENDTCFQ;
ARCHITECTUREARTOFTCFQIS
BEGIN
PROCESS(CLK)
BEGIN
IF(CLK'EVENTANDCLK=‘1’)THEN
Q<=NOT(Q);
ELSEQ<=Q;
ENDIF;
ENDPROCESS;
ENDART;
比较器
ENTITYCOMP_BADIS
PORT(a1,b1:
INBIT;
q1:
OUTBIT);
END;
ARCHITECTUREoneOFCOMP_BADIS
BEGIN
PROCESS(a1,b1)
BEGIN
IFa1>b1THENq1<='1';
ELSIFa1 时,q1作何操作 ENDIF; ENDPROCESS; END; 【例4.9】8位数值比较器的VHDL描述 LIBRARYIEEE; USEIEEE.STD_LOGIC_VECTOR(7DOWNTO0); ENTITYCOMPAREIS PORT(A,B: INSTD_LOGIC_VECTOR(7DOWNTO0); EQ: OUTSTD_LOGIC); ENDCOMPARE; ARCHITECTUREARTOFCOMPAREIS BEGIN EQ<=‘1’WHENA=BELSE‘0’; ENDART; 计数器 LIBRARYIEEE; USEIEEE.STD_LOGIC_1164.ALL; USEIEEE.STD_LOGIC_UNSIGNED.ALL; ENTITYCNT10IS PORT(CLK,RST,EN: INSTD_LOGIC; CQ: OUTSTD_LOGIC_VECTOR(3DOWNTO0); COUT: OUTSTD_LOGIC); ENDCNT10; ARCHITECTUREbehavOFCNT10IS BEGIN PROCESS(CLK,RST,EN) VARIABLECQI: STD_LOGIC_VECTOR(3DOWNTO0); BEGIN IFRST='1'THENCQI: =(OTHERS=>'0');--计数器异步复位 ELSIFCLK'EVENTANDCLK='1'THEN--检测时钟上升沿 IFEN='1'THEN--检测是否允许计数(同步使能) IFCQI<9THENCQI: =CQI+1;--允许计数,检测是否小于9 ELSECQI: =(OTHERS=>'0');--大于9,计数值清零 ENDIF; ENDIF; ENDIF; IFCQI=9THENCOUT<='1';--计数大于9,输出进位信号 ELSECOUT<='0'; ENDIF; CQ<=CQI;--将计数值向端口输出 ENDPROCESS; ENDbehav; 1.同步计数器 【例4.32】一个模为60,具有异步复位、同步置数功能的8421BCD码计数器。 LIBRARYIEEE; USEIEEE.STD_LOGIC_1164.ALL; USEIEEE.STD_LOGIC_UNSIGNED.ALL; ENTITYCNTM60IS PORT(CI: INSTD_LOGIC; NRESET: INSTD_LOGIC; LOAD: INSTD_LOGIC; D: INSTD_LOGIC_VECTOR(7DOWNTO0); CLK: INSTD_LOGIC; CO: OUTSTD_LOGIC; QH: BUFFERSTD_LOGIC_VECTOR(3DOWNTO0); QL: BUFFERSTD_LOGIC_VECTOR(3DOWNTO0)); ENDCNTM60; ARCHITECTUREARTOFCNTM60IS BEGIN CO<=‘1’WHEN(QH="0101"ANDQL="1001"ANDCI=‘1’)ELSE'0'; --进位输出的产生 PROCESS(CLK,NRESET) BEGIN IF(NRESET=‘0’)THEN--异步复位 QH<="0000"; QL<="0000"; ELSIF(CLK'EVENTANDCLK=‘1’)THEN--同步置数 IF(LOAD=‘1’)THEN QH<=D(7DOWNTO4) QL<=D(3DOWNTO0); ELSIF(CI=‘1’)THEN--模60的实现 IF(QL=9)THEN QL<="0000"; IF(QH=5)THEN QH<="0000"; ELSE--计数功能的实现 QH<=QH+1; ENDIF ELSE QL<=QL+1; ENDIF; ENDIF;--ENDIFLOAD ENDPROCESS; ENDART; 一个由8个触发器构成的异步计数器,采用元件例化的方式生成。 LIBRARYIEEE; USEIEEE.STD_LOGIC_1164.ALL; ENTITYDIFFRIS PORT(CLK,CLR,D: INSTD_LOGIC; Q,QB;OUTSTD_LOGIC); ENDDIFFR; ARCHITECTUREART1OFDIFFRIS SIGNALQ_IN: STD_LOGIC; BEGIN Q<=Q_IN; QB<=NOTQ_IN; PROCESS(CLK,CLR) BEGIN IF(CLR=‘1’)THEN Q_IN<=‘0’; ELSIF(CLK'EVENTANDCLK=‘1')THEN Q_IN<=D; ENDIF; ENDPROCESS; ENDART1; LIBRARYIEEE; USEIEEE.STD_LOGIC_1164.ALL; ENTITYRPLCOUNTIS PORT(CLK,CLR: INSTD_LOGIC; COUNT: OUTSTD_LOGIC_VECTOR(7DOWNTO0)); ENDRPLCOUNT; ARCHITECTUREART2OFRPLCOUNTIS SIGNALCOUNT_IN: STD_LOGIC_VECTOR(8DOWNTO0); COMPONENTDIFFR PORT(CLK,CLR,D: INSTD_LOGIC; Q,QB: OUTSTD_LOGIC); ENDCOMPONENT; BEGIN COUNT_IN(0)<=CLK; GEN1: FORIIN0TO7GENERATE U: DIFFRPORTMAP(CLK=>COUNT_IN(I), CLR=>CLR,D=>COUNT_IN(I+1), Q=>COUNT_IN(I),QB=>COUNT_IN(I+1)); ENDGENERATE; ENDART2; 4.188421编码的异步十进制减法计数器 源程序: libraryieee; useieee.std_logic_1164.all; useieee.std_logic_arith.all; useieee.std_logic_unsigned.all; entityh36is port(cp: instd_logic; q: outstd_logic_vector(3downto0); endh36; architecturewofh36is typestateis(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9); signalp: state; signaln: state; signalqn: std_logic_vector(3downto0); begin process(cp) begin ifcp\'eventandcp=\'1\'then p<=n; endif; endprocess; process(p) begin casepis whens0=>n=<=s1; qn<=\"1001\"; whens1=>n=<=s2; qn<=\"1000\"; whens2>n=<=s3; qn<=\"0111\"; whens3=>n=<=s4; qn<=\"0110\";( whens4=>n=<=s5; qn<=\"0101\"; whens5=>n=<=s6; qn<=\"0100\"; whens6=>n=<=s7; qn<=\"0011\"; whens7=>n=<=s8; qn<=\"0010\"; whens8=>n=<=s9; qn<=\"0001\"; whens9=>n=<=s0; qn<=\"0000\"; whenother=>n=<=s0; endcase; endpricess; q<=qn; endw; 【例4.34】用VHDL描述的8位二进制加减计数器源程序。 LIBRARYIEEE; USEIEEE.STD_LOGIC_1164.ALL; ENTITYupdowncnt8IS PORT(clr,clk,ena,load,updown: INSTD_LOGIC; d: ININTEGERRANGE0TO255; cout: OUTSTD_LOGIC; q: BUFFERINTEGERRANGE0TO255); ENDupdowncnt8; ARCHITECTUREoneOFupdowncnt8IS BEGIN PROCESS(clk,ena,clr,d,load,updown) BEGIN IFCLR='0'THENq<=0; ELSIFclk'EVENTANDclk='1'THEN IFload='1'THENq<=d; ELSIFena='1'THEN IFupdown='0'THENq<=q+1; IFq=255THENCOUT<='1';ENDIF; ELSEq<=q-1; IFq=0THENCOUT<='0';ENDIF; ENDIF; ENDIF; ENDIF; ENDPROCESS; ENDone; 移位寄存器2 LibraryIEEE; USEIEEE.STD_LOGIC_1164.ALL; ENTITYSHIFTIS PORT(CLK,C0: INSTD_LOGIC;--时钟和进位输入 MD: INSTD_LOGIC_VECTOR(2DOWNTO0);--移位模式控制字 D: INSTD_LOGIC_VECTOR(7DOWNTO0);--待加载移位的数据 QB: OUTSTD_LOGIC_VECTOR(7DOWNTO0);--移位数据输出 CN: OUTSTD_LOGIC);--进位输出 ENDENTITY; ARCHITECTUREBEHAVOFSHIFTIS SIGNALREG: STD_LOGIC_VECTOR(7DOWNTO0); SIGNALCY: STD_LOGIC; BEGIN PROCESS(CLK,MD,C0) BEGIN IFCLK‘EVENTANDCLK=’1‘THEN接下 CASEMDIS WHEN"001"=>REG(0)<=C0; REG(7DOWNTO1)<=REG(6DOWNTO0);CY<=REG(7);--带进位循环左移 WHEN"010"=>REG(0)<=REG(7); REG(7DOWNTO1)<=REG(6DOWNTO0);--自循环左移 WHEN"011"=>REG(7)<=REG(0); REG(6DOWNTO0)<=REG(7DOWNTO1);--自循环右移 WHEN"100"=>REG(7)<=C0; REG(6DOWNTO0)<=REG(7DOWNTO1);CY<=REG(0);--带进位循环右移 WHEN"101"=>REG(7DOWNTO0)<=D(7DOWNTO0);--加载待移数 WHENOTHERS=>REG<=REG;CY<=CY;--保持 ENDCASE; ENDIF; ENDPROCESS; QB(7DOWNTO0)<=REG(7DOWNTO0);CN<=CY;--移位后输出 ENDBEHAV; ENDbehav; 单进程Moore状态机 ARCHITECTUREbehavOFMOORE1IS TYPEST_TYPEIS(ST0,ST1,ST2,ST3,ST4); SIGNALC_ST: ST_TYPE; BEGIN PROCESS(CLK,RST) BEGIN IFRST='1'THENC_ST<=ST0;Q<="0000"; ELSIFCLK'EVENTANDCLK='1'THEN CASEC_STIS WHENST0=>IFDATAIN="10" THENC_ST<=ST1;ELSEC_ST<=ST0; ENDIF;Q<="1001"; WHENST1=>IFDATAIN="11"THENC_ST<=ST2; ELSEC_ST<=ST1;ENDIF; Q<="0101"; WHENST2=>IFDATAIN="01"THENC_ST<=ST3; ELSEC_ST<=ST0;ENDIF; Q<="1100"; WHENST3=>IFDATAIN="00"THENC_ST<=ST4; ELSEC_ST<=ST2;ENDIF; Q<="0010"; WHENST4=>IFDATAIN="11"THENC_ST<=ST0; ELSEC_ST<=ST3;ENDIF; Q<="1001"; WHENOTHERS=>C_ST<=ST0; ENDCASE; ENDIF; ENDPROCESS; ENDbehav; Mealy状态机 LIBRARYIEEE; USEIEEE.STD_LOGIC_1164.ALL; ENTITYMEALY1IS PORT(CLK,DATAIN,RESET: INSTD_LOGIC; Q: OUTSTD_LOGIC_VECTOR(4DOWNTO0)); ENDMEALY1; ARCHITECTUREbehavOFMEALY1IS TYPEstatesIS(st0,st1,st2,st3,st4); SIGNALSTX: states; BEGIN COMREG: PROCESS(CLK,RESET)BEGIN--决定转换状态的进程 IFRESET='1'THENSTX<=ST0; ELSIFCLK'EVENTANDCLK='1'THENCASESTXIS WHENst0=>IFDATAIN='1'THENSTX<=st1;ENDIF; WHENst1=>IFDATAIN='0'THENSTX<=st2;ENDIF; WHENst2=>IFDATAIN='1'THENSTX<=st3;ENDIF; WHENst3=>IFDATAIN='0'THENSTX<=st4;ENDIF; WHENst4=>IFDATAIN='1'THENSTX<=st0;ENDIF; WHENOTHERS=>STX<=st0; ENDCASE; ENDIF; ENDPROCESSCOMREG; COM1: PROCESS(STX,DATAIN)BEGIN--输出控制信号的进程 CASESTXIS WHENst0=>IFDATAIN='1'THENQ<="10000"; ELSEQ<="01010";ENDIF; WHENst1=>IFDATAIN='0'THENQ<="10111"; ELSEQ<="10100";ENDIF; WHENst2=>IFDATAIN='1'THENQ<="10101"; ELSEQ<="10011";ENDIF; WHENst3=>IFDATAIN='0'THENQ<="11011"; ELSEQ<="01001";ENDIF; WHENst4=>IFDATAIN='1'THENQ<="11101"; ELSEQ<="01101";ENDIF; WHENOTHERS=>Q<="00000"; ENDCASE; ENDPROCESSCOM1; ENDbehav; Mealy状态机 LIBRARYIEEE;--MEALYFSM USEIEEE.STD_LOGIC_1164.ALL; ENTITYMEALY2IS PORT(CLK,DATAIN,RESET: INSTD_LOGIC; Q: OUTSTD_LOGIC_VECTOR(4DOWNTO0)); ENDMEALY2; ARCHITECTUREbehavOFMEALY2IS TYPEstatesIS(st0,st1,st2,st3,st4); SIGNALSTX: states; SIGNALQ1: STD_LOGIC_VECTOR(4DOWNTO0); BEGIN COMREG: PROCESS(CLK,RESET)--决定转换状态的进程 (接下页) BEGIN IFRESET='1'THENSTX<=ST0; ELSIFCLK'EVENTANDCLK='1'THEN CASESTXIS WHENst0=>IFDATAIN='1'THENSTX<=st1;ENDIF; WHENst1=>IFDATAIN='0'THENSTX<=st2;ENDIF; WHENst2=>I
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