完整版毕业设计英文文献51单片机中英文文献翻译.docx

完整版毕业设计英文文献51单片机中英文文献翻译.docx

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完整版毕业设计英文文献51单片机中英文文献翻译

AT89C51的概况

TheGeneralSituationofAT89C51

Chapter1TheapplicationofAT89C51

Microcontrollersareusedinamultitudeofcommercialapplicationssuchasmodems,motor-controlsystems,airconditionercontrolsystems,automotiveengineandamongothers.Thedomainsalsorequirethatthesemicrocontrollersarebeensuredbyarobusttestingprocessandapropertoolsenvironmentforthevalidationofthesemicrocontrollersbothatthecomponentandatthesystemlevel.IntelPlaformEngineeringdepartmentdevelopedanobject-orientedmulti-threadedtestenvironmentforthevalidationofitsAT89C51automotivemicrocontrollers.ThegoalsofthisenvironmentwasnotonlytoprovidearobusttestingenvironmentfortheAT89C51automotivemicrocontrollers,buttodevelopanenvironmentwhichcanbeeasilyextendedandreusedforthevalidationofseveralotherfuturemicrocontrollers.TheenvironmentwasdevelopedinconjunctionwithMicrosoftFoundationClasses（AT89C51）.Thepaperdescribesthedesignandmechanismofthistestenvironment,itsinteractionswithvarious

The8-bitAT89C51CHMOSmicrocontrollersaredesignedtoengine-controlsystems,airbags,suspensionsystems,andantilockbrakingsystems（ABS）.TheAT89C51isespeciallywellsuitedtoapplicationsthatbenefitfromitsprocessingspeedandenhancedon-chipperipheralfunctionsset,suchasautomotivepower-traincontrol,vehicledynamicsuspension,antilockbraking,andstabilitycontrolapplications.Becauseofthesecriticalapplications,themarketrequiresareliablecost-effectivecontrollerwithalowinterruptlatencyresponse,abilitytoservicetheintegratedperipheralsneededinrealtimeapplications,andaCPUwithaboveaverageprocessingpowerinasinglepackage.Thefinancialandlegalriskofthemarket,particularlyinmissioncriticalapplicationssuchasanautopilotoranti-lockbrakingsystem,mistakesarefinanciallyprohibitive.Redesigncostscanrunasflaw.Inaddition,fieldreplacementsofcomponentsisextremelyexpensive,asthedevicesaretypicallysealedinmoduleswithatotalvalueseveraltimesthatofthecomponent.Tomitigatetheseproblems,itisessentialthatcomprehensivetestingofthecontrollersbecarriedoutatboththecomponentlevelandsystemlevelunderworstcaseenvironmentalandvoltageconditions.Thiscompleteandthoroughvalidationnecessitatesnotonlyawell-definedprocessbutalsoaproperenvironmentandtoolstofacilitateandexecutethemissionsuccessfully.IntelChandlerPlatformEngineeringgroupprovidespostsiliconsystemvalidation（SV）ofvariousmicro-controllersandprocessors.Thesystemvalidationprocesscanbebrokenintothreemajorparts.Thetypeofthedeviceanditsapplicationrequirementsdeterminewhichtypesoftestingareperformedonthedevice.

1.2TheAT89C51providesthefollowingstandardfeatures:

4KbytesofFlash,128bytesofRAM,32IOlines,two16-bittimercounters,afivevectortwo-levelinterruptarchitecture,afulldupleser-ialport,on-chiposcillatorandclockcircuitry.Inaddition,theAT89C51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timercounters,serialportandinterruptsys-temtocontinuefunctioning.ThePower-downModesavestheRAMcontentsbutfreezestheoscil–latordisablingallotherchipfunctionsuntilthenextDescription

VCCSupplyvoltage.

GNDGround.

Port0：

Port0isan8-bitopen-drainbi-directionalIOport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedasthismodeP0.Externalpullupsarerequiredduringprogramverification.

Port1：

Port1isan8-bitbi-directionalIOportwithinternalpullups.ThePort1outputbufferscansinkso-urcefourTTLinputs.When1sarewrittentoPort1pinstheyarepulledbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent（IIL）becauseoftheinternalpullups.Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.

Port2：

Port2isan8-bitbi-directionalIOportwithinternalpullups.ThePort2outputbufferscansinksourcefourTTLinputs.When1sarewrittentoPort2pinstheyarepulledbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent（IIL）becauseoftheinternalpullups.Port2emitsthethisapplication,itusesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses（MOVX@RI）,Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivestheFlashprogrammingandverification.

Port3：

Port3isan8-bitbi-directionalIOportwithinternalpullups.ThePort3outputbufferscansinksou-rcefourTTLinputs.When1sarewrittentoPort3pinstheyarepulledbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent（IIL）becauseofthepullups.

Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89C51aslistedbelow:

RST：

Resetinput.Athispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.

ALEPROG：

AddressLatchEnableoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput（PROG）duringFlashprogramming.InnormaloperationALEisemittedataconstantrateof16theoscillatorfrequency,andmaybeusedforexternaltimingorclockingpurposes.Note,bedisabledbysettingbit0ofSFRlocation8EH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledexternalexecutionmode.

PSEN：

ProgramStoreEnableisthereadstrobetoexternalprogrammemory.WhentheAT89C51isexecutingcodefromexternalprogrammemory,PSENisactivatedtwiceeachmachinecycle,exceptthattwoPSENactivationsareskippedduringeachaccesstoexternaldatamemory.

EAVPP：

ExternalAccessEnable.EAmustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFH.Note,alsreceivesthe12-voltprogrammingenablevoltage（VPP）duringFlashprogramming,forpartsthatrequire12-voltVPP.

XTAL1：

Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit.

XTAL2：

Outputfromtheinvertingoscillatoramplifier.OscillatorCharacteristicsXTAL1andXTAL2aretheinputandoutput,respectively,ofaninvertingamplifierwhichcanbeconfiguredforuseasanon-chiposcillator,asshowninFigure1.Eitheraquartzcrystalorceramicresonatormaybeused.Todrivethedevicefromanexternalclocksource,XTAL2shouldbeleftunconnectedwhileXTAL1isdrivenasshowninFigure2.Therearenorequirementsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclockingcircuitryisthroughadivide-by-twoflip-flop,butminimumandmaximumvoltageidlemode,theCPUputsitselftosleepwhilealltheonchipperipheralsremainactive.Themodeisinvokedbysoftware.Thecontentoftheon-chipRAMandallthespecialfunctionsregistersremainunchangedduringthismode.Theidlemodecanbeterminatedbyanyenabledinterruptorbyaidleisterminatedbya,fromwhereitleftoff,uptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrol.On-chipthisevent,butaccesstotheportpinsisnotinhibited.ToeliminatethepossibilityofanunexpectedwritetoaportpinwhenIdleisterminatedbyreset,theinstructionfollowingtheonethatinvokesIdleshouldnotbeonethatwritestoaportpinortoexternalmemory.

Power-downMode

Inthepower-downmode,theoscillatorisstopped,andtheinstructionthatinvokespower-downisthelastinstructionexecuted.Theon-chipRAMandSpecialFunctionRegistersretaintheirvaluesuntilthepower-downmodeisterminated.Theonlyexitfrompower-downisa-chipRAM.TheresetshouldnotbeactivatedbeforeVCCisrestoredtoitsnormaloperatinglevelandmustbeeitherprogrammingmode.Toprogramanynonblankbyteintheon-chipFlashMemory,theentirememorymustbeerasedusingtheChipEraseMode.

2ProgrammingAlgorithm

BeforeprogrammingtheAT89C51,theaddress,dataandcontrolsignalsshouldbesetupaccordingtotheFlashprogrammingmodetableandFigure3andFigure4.ToprogramtheAT89C51,takethefollowingsteps.1.Inputthedesiredmemorylocationontheaddresslines.2.Inputtheappropriatedatabyteonthedatalines.3.Activatethecorrectcombinationofcontrolsignals.4.RaiseEAVPPto12VforthetheFlasharrayorthelockbits.Thebyte-writecycleisself-timedandtypicallytakesnomorethan1.5ms.Repeatsteps1through5,changingtheaddressanddatafortheentirearrayoruntiltheendoftheobjectfileisreached.DataPolling:

TheAT89C51featuresDataPollingtoindicatetheendofawritecycle.Duringawritecycle,anattemptedreadofthelastbytewrittenwillresultinthecomplementofthewrittendatumonPO.7.Oncethewritecyclecompleted,truedataarevalidonalloutputs,andthenextcyclemaybegin.DataPollingmaybeginanytimeafterawritecycleinitiated.

2.1ReadyBusy:

TheprogressofbyteprogrammingcanalsobemonitoredbytheRDYBSYoutputsignal.P3.4ispulledlowafterALEgoeswhenprogrammingisdonetoindicateREADY.

ProgramVerify:

IflockbitsLB1andLB2programmed,theprogrammedcodedatacanbereadbackviatheaddressanddatalinesforverification.Thelockbitscannotbeverifieddirectly.Verificationofthelockbitsisachievedbyobservingthattheirfeaturesareenabled.

Figure2-1-1ProgrammingtheFlashFigure2-2-2VerifyingtheFlash

2.2ChipErase:

Theentire