DDS波形发生器VHDL源码.docx
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DDS波形发生器VHDL源码.docx
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DDS波形发生器VHDL源码
--DDS波形发生器(Synplifypro编译通过)
--输出频率Fout=Fclk*2^M/2^N
--分辨率Fclk/2^N
--最大输出频率Fout=Fclk*50%(理论值,抽样定理)
--版本1.0 2004/9/29 byJJJ
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityDDSis
generic(ACCWidth:
Integer:
=16); --相位累加器的长度2^N(2^ACCWidth)
port(
CLK:
instd_logic; --系统时钟FClk
STEP:
instd_logic_vector(ACCWidth-1downto0); --步进,即相位累加器的累加增量,控制输出频率2^M频率控制字
CHOICE:
instd_logic_vector(1downto0); --波形选择信号 "00":
正弦; "01":
三角波; "10":
方波; "11":
不输出(恒为低电平)
-- DAOUT:
outstd_logic_vector(7downto0); --8位DA输出模拟信号,直通方式,如需时钟控制则要修改
DAOUTX:
outstd_logic_vector(7downto0);
DAOUTY:
outstd_logic_vector(7downto0)
);
end;
architectureDDSofDDSis
signalACC:
std_logic_vector(ACCWidth-1downto0):
=(others=>'0');
signalDAOUT:
std_logic_vector(7downto0);
begin
process(CLK,STEP)
begin
if(CLK'eventandCLK='1')then
ACC<=ACC+STEP;
endif;
endprocess;
process(CHOICE,ACC)
begin
caseCHOICEis
when"00"=> --正弦
caseACC(ACCWidth-1downtoACCWidth-8)is
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