习题四位乘法器的设计.docx
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习题四位乘法器的设计.docx
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习题四位乘法器的设计
习题二、四位乘法器的设计
⏹问题说明:
⏹每个学生根据自己的对于乘法运算和乘法器设计的理解,进行乘法器电路的设计,并用FPGA实现之。
仅要求能够实现四位BIT的乘法运算,其他不作约束,根据自己的理解和兴趣,自由定义。
⏹设计实验要求:
⏹1.各自自行定义和设计,互相要有差异化,说明自己的定义特征和设计思想,要求设计至少一种电路去实现.
⏹2.对于自行设计有特色和原理说明详细的实验,即使实现结果有局部错误,也给予高分评价。
⏹3.要求设计实验报告内容包括:
设计定义说明、电路图、功能仿真和时序仿真图、实现后的有关资源利用等REPORT文件内容摘要。
图为:
四位乘法器一个数的高四位与另一个数的低两位乘累加器
图为:
一位全加器
图为:
四位乘法器一个数的高四位与另一个数的高两位乘累加器
图为:
将四位二进制乘数与低两位二进制数相乘累加结果与另一组四位二进制乘数与高两位二进制数相乘累加结果进行相加,最后计算出四位与四位相乘的结果。
功能仿真结果:
通过原理图的输入,后经过功能上的仿真输出了以下原理图VHDL的功能实现代码。
libraryieee;
useieee.std_logic_1164.ALL;
useieee.numeric_std.ALL;
--synopsystranslate_off
libraryUNISIM;
useUNISIM.Vcomponents.ALL;
--synopsystranslate_on
entityfour_bit_mul3is
port(a0:
instd_logic;
a1:
instd_logic;
a2:
instd_logic;
a3:
instd_logic;
b0:
instd_logic;
b1:
instd_logic;
b2:
instd_logic;
b3:
instd_logic;
clk:
instd_logic;
clr:
instd_logic;
S1:
outstd_logic;
s2:
outstd_logic;
s3:
outstd_logic;
s4:
outstd_logic;
s5:
outstd_logic;
s6:
outstd_logic;
s7:
outstd_logic;
s8:
outstd_logic);
endfour_bit_mul3;
architectureBEHAVIORALoffour_bit_mul3is
attributeBOX_TYPE:
string;
signalXLXN_68:
std_logic;
signalXLXN_101:
std_logic;
signalXLXN_103:
std_logic;
signalXLXN_104:
std_logic;
signalXLXN_105:
std_logic;
signalXLXN_106:
std_logic;
signalXLXN_107:
std_logic;
signalXLXN_108:
std_logic;
signalXLXN_109:
std_logic;
signalXLXN_110:
std_logic;
signalXLXN_119:
std_logic;
signalXLXN_120:
std_logic;
signalXLXN_129:
std_logic;
signalXLXN_130:
std_logic;
signalXLXN_131:
std_logic;
componentfourbit_mul
port(clr:
instd_logic;
a3:
instd_logic;
a2:
instd_logic;
a1:
instd_logic;
b0:
instd_logic;
b1:
instd_logic;
clk:
instd_logic;
a0:
instd_logic;
out1:
outstd_logic;
out2:
outstd_logic;
add1:
outstd_logic;
add2:
outstd_logic;
add3:
outstd_logic;
add4:
outstd_logic);
endcomponent;
componentfoutbit_mul1
port(clr:
instd_logic;
a1:
instd_logic;
a0:
instd_logic;
a2:
instd_logic;
a3:
instd_logic;
b2:
instd_logic;
b3:
instd_logic;
clk:
instd_logic;
add1_1:
outstd_logic;
add2_1:
outstd_logic;
add3_1:
outstd_logic;
out8:
outstd_logic;
out9:
outstd_logic;
add4_1:
outstd_logic);
endcomponent;
componentmul
port(A:
instd_logic;
B:
instd_logic;
Cin:
instd_logic;
S:
outstd_logic;
Cout:
outstd_logic);
endcomponent;
componentGND
port(G:
outstd_logic);
endcomponent;
attributeBOX_TYPEofGND:
componentis"BLACK_BOX";
begin
XLXI_1:
fourbit_mul
portmap(a0=>a0,
a1=>a1,
a2=>a2,
a3=>a3,
b0=>b0,
b1=>b1,
clk=>clk,
clr=>clr,
add1=>XLXN_101,
add2=>XLXN_105,
add3=>XLXN_107,
add4=>XLXN_110,
out1=>S1,
out2=>s2);
XLXI_2:
foutbit_mul1
portmap(a0=>a0,
a1=>a1,
a2=>a2,
a3=>a3,
b2=>b2,
b3=>b3,
clk=>clk,
clr=>clr,
add1_1=>XLXN_103,
add2_1=>XLXN_106,
add3_1=>XLXN_108,
add4_1=>XLXN_119,
out8=>XLXN_129,
out9=>s8);
XLXI_3:
mul
portmap(A=>XLXN_101,
B=>XLXN_103,
Cin=>XLXN_68,
Cout=>XLXN_104,
S=>s3);
XLXI_4:
mul
portmap(A=>XLXN_105,
B=>XLXN_106,
Cin=>XLXN_104,
Cout=>XLXN_109,
S=>s4);
XLXI_5:
mul
portmap(A=>XLXN_107,
B=>XLXN_108,
Cin=>XLXN_109,
Cout=>XLXN_120,
S=>s5);
XLXI_14:
GND
portmap(G=>XLXN_68);
XLXI_18:
mul
portmap(A=>XLXN_110,
B=>XLXN_119,
Cin=>XLXN_120,
Cout=>XLXN_130,
S=>s6);
XLXI_19:
mul
portmap(A=>XLXN_130,
B=>XLXN_129,
Cin=>XLXN_131,
Cout=>open,
S=>s7);
XLXI_21:
GND
portmap(G=>XLXN_131);
endBEHAVIORAL;
时序仿真:
一位全加法器:
四位与低两位乘法器:
四位与高两位乘法器:
最后结果:
完整的综合仿真报告:
Release7.1i-xstH.38
Copyright(c)1995-2005Xilinx,Inc.Allrightsreserved.
-->ParameterTMPDIRsetto__projnav
CPU:
0.00/0.23s|Elapsed:
0.00/0.00s
-->Parameterxsthdpdirsetto./xst
CPU:
0.00/0.23s|Elapsed:
0.00/0.00s
-->Readingdesign:
four_bit_mul3.prj
TABLEOFCONTENTS
1)SynthesisOptionsSummary
2)HDLCompilation
3)HDLAnalysis
4)HDLSynthesis
5)AdvancedHDLSynthesis
5.1)HDLSynthesisReport
6)LowLevelSynthesis
7)FinalReport
=========================================================================
*SynthesisOptionsSummary*
=========================================================================
----SourceParameters
InputFileName:
"four_bit_mul3.prj"
InputFormat:
mixed
IgnoreSynthesisConstraintFile:
NO
----TargetParameters
OutputFileName:
"four_bit_mul3"
OutputFormat:
NGC
TargetDevice:
acr2
----SourceOptions
TopModuleName:
four_bit_mul3
AutomaticFSMExtraction:
YES
FSMEncodingAlgorithm:
Auto
MuxExtraction:
YES
ResourceSharing:
YES
----TargetOptions
AddIOBuffers:
YES
EquivalentregisterRemoval:
YES
MACROPreserve:
YES
XORPreserve:
YES
----GeneralOptions
OptimizationGoal:
Speed
OptimizationEffort:
1
KeepHierarchy:
YES
RTLOutput:
Yes
HierarchySeparator:
/
BusDelimiter:
<>
CaseSpecifier:
maintain
----OtherOptions
lso:
four_bit_mul3.lso
verilog2001:
YES
safe_implementation:
No
ClockEnable:
YES
wysiwyg:
NO
=========================================================================
=========================================================================
*HDLCompilation*
=========================================================================
Compilingvhdlfile"E:
/programwork/multiplier/multiplier/mul.vhf"inLibrarywork.
ArchitecturebehavioralofEntitymulisuptodate.
Compilingvhdlfile"E:
/programwork/multiplier/multiplier/fourbit_mul.vhf"inLibrarywork.
ArchitecturebehavioralofEntityfdc_mxilinx_fourbit_mulisuptodate.
ArchitecturebehavioralofEntityfourbit_mulisuptodate.
Compilingvhdlfile"E:
/programwork/multiplier/multiplier/foutbit_mul1.vhf"inLibrarywork.
ArchitecturebehavioralofEntityfdc_mxilinx_foutbit_mul1isuptodate.
ArchitecturebehavioralofEntityfoutbit_mul1isuptodate.
Compilingvhdlfile"E:
/programwork/multiplier/multiplier/four_bit_mul3.vhf"inLibrarywork.
ArchitecturebehavioralofEntityfour_bit_mul3isuptodate.
=========================================================================
*HDLAnalysis*
=========================================================================
AnalyzingEntity
WARNING:
Xst:
753-"E:
/programwork/multiplier/multiplier/four_bit_mul3.vhf"line180:
Unconnectedoutputport'Cout'ofcomponent'mul'.
Entity
AnalyzingEntity
Setuser-definedproperty"HU_SET=XLXI_29_7"forinstance
Setuser-definedproperty"HU_SET=XLXI_30_6"forinstance
Setuser-definedproperty"HU_SET=XLXI_31_5"forinstance
Setuser-definedproperty"HU_SET=XLXI_32_4"forinstance
Setuser-definedproperty"HU_SET=XLXI_41_0"forinstance
Setuser-definedproperty"HU_SET=XLXI_42_3"forinstance
Setuser-definedproperty"HU_SET=XLXI_43_2"forinstance
Setuser-definedproperty"HU_SET=XLXI_44_1"forinstance
Entity
AnalyzingEntity
Entity
AnalyzingEntity
Setuser-definedproperty"HU_SET=XLXI_1_0"forinstance
Setuser-definedproperty"HU_SET=XLXI_2_5"forinstance
Setuser-definedproperty"HU_SET=XLXI_3_8"forinstance
Setuser-definedproperty"HU_SET=XLXI_4_11"forinstance
Setuser-definedproperty"HU_SET=XLXI_5_1"forinstance
Setuser-definedproperty"HU_SET=XLXI_6_4"forinstance
Setuser-definedproperty"HU_SET=XLXI_7_7"forinstance
Setuser-definedproperty"HU_SET=XLXI_8_10"forinstance
Setuser-definedproperty"HU_SET=XLXI_9_2"forinstance
Setuser-definedproperty"HU_SET=XLXI_10_3"forinstance
Setuser-definedproperty"HU_SET=XLXI_11_6"forinstance
Setuser-definedproperty"HU_SET=XLXI_12_9"forinstance
Setuser-definedproperty"HU_SET=XLXI_35_15"forinstance
Setuser-definedproperty"HU_SET=XLXI_36_12"forinstance
Setuser-definedproperty"HU_SET=XLXI_37_13"forinstance
Setuser-definedproperty"HU_SET=XLXI_38_14"forinstance
Entity
AnalyzingEntity
Entity
AnalyzingEntity
Entity
=========================================================================
*HDLSynthesis*
=========================================================================
SynthesizingUnit
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