EDA例子.docx
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EDA例子.docx
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EDA例子
第五章例子
三输入与门
1,
ENTITYandgate3IS
PORT(a,b,c:
INBIT;x:
OUTBIT);
ENDENTITYandgate3;
ARCHITECTUREdataflow2OFandgate3IS
BEGIN
x<=aANDbANDC;
ENDARCHITECTUREdataflow;--(数据流描述)
2,
ENTITYandgate3IS
PORT(a,b,c:
INBIT;y:
OUTBIT);
ENDENTITYandgate3;
ARCHITECTUREbehaviorOFandgate3IS
BEGIN
Comb:
PROCESS(a,b,c)顺序描述语句
BEGIN
IF(a='1'ANDb='1'ANDc='1')THEN分支语句word9页
y<='1';
ELSE
y<='0';
ENDIF;
ENDPROCESSComb;
ENDARCHITECTUREbehavior;--(行为描述)
3,
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYand3_1IS
PORT(a,b,c:
INBIT;
x:
OUTBIT);
ENDENTITYand3_1;
ARCHITECTUREbehavior2OFand3_1IS
SIGNALindata:
bit_vector(2DOWNTO0);
BEGIN
indata<=a&b&c;
Comb1:
PROCESS(a,b,c)因为indata是abc相关,没写入
BEGIN
CASEindataIS分支语句9
WHEN"000"=>x<='0';
WHEN"001"=>x<='0';
WHEN"010"=>x<='0';
WHEN"011"=>x<='0';
WHEN"100"=>x<='0';
WHEN"101"=>x<='0';
WHEN"110"=>x<='0';
WHEN"111"=>x<='1';
ENDCASE;
ENDPROCESSComb1;
ENDARCHITECTUREbehavior2;--行为描述
2输入与非门的VHDL描述
ENTITYnand2IS--实体描述
PORT(i1,i2:
INBIT;--输入信号名
o1:
OUTBIT);--输出信号名
ENDnand2;
ARCHITECTUREdelayedOFnand2IS--结构体描述
BEGIN
o1<=i1NANDi2AFTER5NS;--电路描述
ENDdelayed
二输入与非门的另一种描述。
ARCHITECTUREanotherOFnand2IS
BEGIN
PROCESS(i1,i2)
BEGIN
IFi1='1'ANDi2='1'THEN
o1<='0'AFTER5NS;
ELSEo1<='1'AFTER5NS;
ENDIF;
ENDPROCESS;
ENDanother;
例5.4半加器的数据流描述。
ENTITYhalf_adderIS
PORT(a,b:
INBIT;
s,c0:
OUTBIT);
ENDhalf_adder;
ARCHITECTUREh_adderOFhalf_adderIS
SIGNALc,d:
BIT;
BEGIN信号时非输入输出的中间量相c<=aORb;
d<=aNANDb;当于下一阶段的输入和上一阶段的输出?
c0<=NOTd;
s<=cANDd;
ENDh_adder;
例5.9全加器的结构描述。
使用前面已经定义过的半加器
ENTITYfull_adderIS
PORT(x,y,cin:
INBIT;
sum,carry:
OUTBIT);
ENDfull_adder;
ARCHITECTUREstructOFfull_adderIS
COMPONENThalf_adder部件声明
PORT(a,b:
INBIT;s,c0:
OUTBIT);
ENDCOMPONENT;
SIGNALh1_s,h1_c,h2_c:
BIT;
BEGIN两半加器中间信号
h1:
half_adderPORTMAP(x,y,h1_s,h1_c);部件描述第一种(如x对应声明中的a)
h2:
half_adderPORTMAP(a=>h1_s,b=>cin,s=>sum,c0=>h2_c);
第二种(h2中的a对应h1_s)第一个全家器的输出被第二个的输入对应
carry<=h2_cORh1_c;
ENDstruct;
数据选择器
例5.5用条件赋值语句描述数据选择器。
ENTITYmux4_to_1IS
PORT(d0,d1,d2,d3,a,b:
INBIT;
y:
OUTBIT);
ENDmux4_to_1;
ARCHITECTUREsample_1OFmux4_to_1IS
BEGIN
y<=d0WHENa='0'ANDb='0'ELSE
d1WHENa='0'ANDb='1'ELSE
d2WHENa='1'ANDb='0'ELSE
d3WHENa='1'ANDb='1';
ENDsample_1;
例5.6用信号选择语句描述数据选择器。
ENTITYmux4_to_1IS
PORT(d0,d1,d2,d3,a,b:
INstd_logic;
y:
OUTstd_logic);
ENDmux4_to_1;
ARCHITECTUREsample_2OFmux4_to_1IS
BEGIN
WITHa&bSELECT
y<=d0WHEN"00",
d1WHEN"01",
d2WHEN"10",
d3WHEN"11",
'X'WHENOTHERS;
ENDsample_2;
例5.8四选一数据选择器的顺序描述。
ENTITYmux4_1IS
PORT(a,b,i0,i1,i2,i3:
INBIT;y:
OUTBIT);
ENDmux4_1;
ARCHITECTUREbehaveOFmux4_1IS
SIGNALselbit_vector(1DOWNTO0);信号
BEGIN
sel<=b&a;
PROCESS(sel,i0,i1,i2,i3)
BEGIN
CASEselIS
WHEN"00"=>y<=i0;
WHEN"01"=>y<=i1;
WHEN"10"=>y<=i2;
WHEN"11"=>y<=i3;
ENDCASE;
ENDPROCESS;
ENDbehave
反向器
例5.7反向器的顺序描述。
ENTITYinverterIS
PORT(x:
INBIT;
y:
OUTBIT);
ENDinverter;
ARCHITECTUREbehaveOFinverterIS
BEGIN
PROCESS(x)只用到x作为判断条件
BEGIN
IF(x='0')THENy<=‘1';
ELSEy<=‘0';
ENDIF;
ENDPROCESS;
ENDbehave;
8线—3线编码器
例:
采用行为描述方式的8线—3线编码器
(依据逻辑表达式)
逻辑关系
A2=I4+I5+I6+I7
A1=I2+I3+I6+I7
A0=I1+I3+I5+I7
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYcoder83_v1IS
PORT(I0,I1,I2,I3,I4,I5,I6,I7:
INSTD_LOGIC;
A0,A1,A2:
OUTSTD_LOGIC);
ENDcoder83_v1;
ARCHITECTUREbehaveOFcoder83_v1IS
BEGIN
A2<=I4ORI5ORI6ORI7;
A1<=I2ORI3ORI6ORI7;
A0<=I1ORI3ORI5ORI7;
ENDbehave;
例:
采用数据流描述方式的8线—3线编码器VHDL源代
码(依据真值表)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYcoder83_v2IS
PORT(I:
INSTD_LOGIC_VECTOR(7DOWNTO0);
A:
OUTSTD_LOGIC_VECTOR(2DOWNTO0));
ENDcoder83_v2;
ARCHITECTUREdataflowOFcoder83_v2IS
BEGIN
PROCESS(I)
BEGIN
CASEIIS
WHEN"10000000"=>A<="111";
WHEN"01000000"=>A<="110";
WHEN"00100000"=>A<="101";
WHEN"00010000"=>A<="100";
WHEN"00001000"=>A<="011";
WHEN"00000100"=>A<="010";
WHEN"00000010"=>A<="001";
WHENOTHERS=>A<="000";
ENDCASE;
ENDPROCESS;
ENDdataflow;
三、优先编码器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYprioritycoder83_v1IS
PORT(I7,I6,I5,I4,I3,I2,I1,I0:
INSTD_LOGIC;
EI:
INSTD_LOGIC;
A2,A1,A0:
OUTSTD_LOGIC;
GS,EO:
OUTSTD_LOGIC);
ENDprioritycoder83_v1;
ARCHITECTUREbehaveOFprioritycoder83_v1IS
BEGIN
A2<=EIOR(I7ANDI6ANDI5ANDI4);
A1<=EIOR(I7ANDI6ANDI3ANDI2)
OR(I7ANDI6ANDNOTI5)
OR(I7ANDI6ANDNOTI4);
A0<=EIOR(I7ANDNOTI6)
OR(I7ANDI5ANDNOTI4)
OR(I7ANDI5ANDI3ANDI1)
OR(I7ANDI5ANDI3ANDNOTI2);
GS<=EIOR(I7ANDI6ANDI5ANDI4ANDI3
ANDI2ANDI1ANDI0);
EO<=EIORNOT(I7ANDI6ANDI5
ANDI4ANDI3ANDI2ANDI1ANDI0);
ENDbehave;
译码器
按数据流描述方式编写的3线—8线译码器74138VHDL
源代码
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYdecoder138_v2IS
PORT(G1,G2A,G2B:
INSTD_LOGIC;
A:
INSTD_LOGIC_VECTOR(2DOWNTO0);
Y:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDdecoder138_v2;
ARCHITECTUREdataflowOFdecoder138_v2IS
BEGIN
PROCESS(G1,G2A,G2B,A)
BEGIN
IF(G1='1'ANDG2A='0'ANDG2B='0')THEN
CASEAIS
WHEN"000"=>Y<="11111110";
WHEN"001"=>Y<="11111101";
WHEN"010"=>Y<="11111011";
WHEN"011"=>Y<="11110111";
WHEN"100"=>Y<="11101111";
WHEN"101"=>Y<="11011111";
WHEN"110"=>Y<="10111111";
WHENOTHERS=>Y<="01111111";
ENDCASE;
ELSEY<="11111111";
ENDIF;
ENDPROCESS;
ENDdataflow;
多路选择器
参考74151的真值表,采用IF语句结构编写的
VHDL源代码如下:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux8_v2IS
PORT(A:
INSTD_LOGIC_VECTOR(2DOWNTO0);
D0,D1,D2,D3,D4,D5,D6,D7:
INSTD_LOGIC;
G:
INSTD_LOGIC;
Y:
OUTSTD_LOGIC;
YB:
OUTSTD_LOGIC);
ENDmux8_v2;
ARCHITECTUREdataflowOFmux8_v2IS
BEGIN
PROCESS(A,D0,D1,D2,D3,D4,D5,D6,D7,G)
BEGIN
IF(G='1')THEN
Y<='0';
YB<='1';
ELSEIF(G='0'ANDA="000")THEN
Y<=D0;
YB<=NOTD0;
ELSIF(G='0'ANDA="001")THEN太长,一部分
Y<=D1;
YB<=NOTD1;
ENDIF;
ENDPROCESS;
ENDdataflow;
数值比较器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYcomp4_v1IS
PORT(A:
INSTD_LOGIC_VECTOR(3DOWNTO0);
B:
INSTD_LOGIC_VECTOR(3DOWNTO0);
YA,YB,YC:
OUTSTD_LOGIC);
ENDcomp4_v1;
ARCHITECTUREbehaveOFcomp4_v1IS
BEGIN
PROCESS(A,B)
BEGIN
IF(A>B)THEN
YA<='1';
YB<='0';
YC<='0';
ELSIF(A
YA<='0';
YB<='1';
YC<='0';
ELSE
YA<='0';
YB<='0';
YC<='1';
ENDIF;
ENDPROCESS;
ENDbehave;
加法器
LBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYadder8_vIS
PORT(A:
INSTD_LOGIC_VECTOR(7DOWNTO0);
B:
INSTD_LOGIC_VECTOR(7DOWNTO0);
Cin:
INSTD_LOGIC;
Co:
OUTSTD_LOGIC;
S:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDadder8_v;
ARCHITECTUREbehaveOFadder8_vIS
SIGNALSint:
STD_LOGIC_VECTOR(8DOWNTO0);
SIGNALAA,BB:
STD_LOGIC_VECTOR(8DOWNTO0);
BEGIN
AA<='0'&A(7DOWNTO0);
BB<='0'&B(7DOWNTO0);
Sint<=AA+BB+Cin;
S(7DOWNTO0)<=Sint(7DOWNTO0);
Co<=Sint(8);
ENDbehave;
分频(重要)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_unsigned.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYfenpinIS
PORT(clk:
INSTD_LOGIC;
sd:
INSTD_LOGIC;
EN:
INSTD_LOGIC;
clk_F:
OUTSTD_LOGIC;
sd_1:
OUTSTD_LOGIC;
wx:
OUTSTD_LOGIC;
EN_1:
OUTSTD_LOGIC
);
ENDfenpin;
ARCHITECTUREg1OFfenpinIS
SIGNALclk_DIV:
STD_LOGIC;
BEGIN
PROCESS(clk)
VARIABLECOUNT:
INTEGERRANGE0TO4;
BEGIN
IF(clk'EVENTANDclk='1')THEN
IF(COUNT=3)THEN
COUNT:
=0;
ELSECOUNT:
=COUNT+1;
IF(COUNT<2)THEN
clk_DIV<='1';
ELSEclk_DIV<='0';
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
clk_F<=clk_DIV;
EN_1<=EN;
sd_1<=sd;
wx<=clk;
ENDg1;
按键消除抖动(重要)
libraryIEEE;
useieee.std_logic_1164.all;
entityxiaodouis
port(
clk,key,xuan:
instd_logic;
dmc,clk_out,xuan_out:
outstd_logic
);
endxiaodou;
architectureg0ofxiaodouis
signalr,s,qr,qs,d1,d2,q1,q2,d3,d4,q3,q4,cp:
std_logic;
begin
process(clk)
begin
if(clk'eventandclk='1')then
d1<=key;
d2<=d1;
q2<=d2;
d3<=qr;
d4<=d3;
q4<=d4;
endif;
r<=(notd2)and(notq2);
s<=d2andq2;
qr<=rnorqs;
qs<=snorqr;
cp<=d4and(notq4);
dmc<=cp;
endprocess;
clk_out<=clk;
xuan_out<=xuan;
endg0;
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