DES算法使用vhdl硬件语言实现.docx
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DES算法使用vhdl硬件语言实现.docx
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DES算法使用vhdl硬件语言实现
libraryieee;
packagedes_libis
ponentdes
port instd_logic; reset: instd_logic; encrypt: instd_logic; key_in: instd_logic_vector<55downto0>; din: instd_logic_vector<63downto0>; din_valid: instd_logic; busy: bufferstd_logic; dout: outstd_logic_vector<63downto0>; dout_valid: outstd_logic >; endponent; ponentdes_round port instd_logic; reset: instd_logic; stall: instd_logic; encrypt_in: instd_logic; encrypt_shift: instd_logic_vector<4downto0>; decrypt_shift: instd_logic_vector<4downto0>; key_in: instd_logic_vector<55downto0>; din: instd_logic_vector<63downto0>; din_valid: instd_logic; encrypt_out: outstd_logic; key_out: outstd_logic_vector<55downto0>; dout: outstd_logic_vector<63downto0>; dout_valid: outstd_logic >; endponent; --Initalpermutation functiondes_ip std_logic_vector<63downto0>> returnstd_logic_vector; --Finalpermutation functiondes_fp std_logic_vector<63downto0>> returnstd_logic_vector; --Keypermutation,convertsa64bitkeyintoa56bitkey,ignoringparity functiondes_kp std_logic_vector<63downto0>> returnstd_logic_vector; --pressionPermutation,convertsa56bitkeyintoa48bits. functiondes_cp std_logic_vector<55downto0>> returnstd_logic_vector; --Expansionpermutation functiondes_ep std_logic_vector<31downto0>> returnstd_logic_vector; --S-BoxSubstitution,48bitsin,32bitsout. functiondes_sbox std_logic_vector<47downto0>> returnstd_logic_vector; --P-BoxPermutation functiondes_pbox std_logic_vector<31downto0>> returnstd_logic_vector; --KeyShift functiondes_keyshift std_logic_vector<55downto0>; n: std_logic_vector<4downto0>> returnstd_logic_vector; enddes_lib; ---------------------------------------------------------------------------- libraryieee; librarywork; packagebodydes_libis -------------------------------------------------------- --Initalpermutation functiondes_ip std_logic_vector<63downto0>> returnstd_logic_vectoris variableval: std_logic_vector<63downto0>; begin val: =din<64-58>&din<64-50>&din<64-42>&din<64-34>&din<64-26>&din<64-18>&din<64-10>&din<64-2>& din<64-60>&din<64-52>&din<64-44>&din<64-36>&din<64-28>&din<64-20>&din<64-12>&din<64-4>& din<64-62>&din<64-54>&din<64-46>&din<64-38>&din<64-30>&din<64-22>&din<64-14>&din<64-6>& din<64-64>&din<64-56>&din<64-48>&din<64-40>&din<64-32>&din<64-24>&din<64-16>&din<64-8>& din<64-57>&din<64-49>&din<64-41>&din<64-33>&din<64-25>&din<64-17>&din<64-9>&din<64-1>& din<64-59>&din<64-51>&din<64-43>&din<64-35>&din<64-27>&din<64-19>&din<64-11>&din<64-3>& din<64-61>&din<64-53>&din<64-45>&din<64-37>&din<64-29>&din<64-21>&din<64-13>&din<64-5>& din<64-63>&din<64-55>&din<64-47>&din<64-39>&din<64-31>&din<64-23>&din<64-15>&din<64-7>; returnval; enddes_ip; -------------------------------------------------------- --Finalpermutation functiondes_fp std_logic_vector<63downto0>> returnstd_logic_vectoris variableval: std_logic_vector<63downto0>; begin val: =din<64-40>&din<64-8>&din<64-48>&din<64-16>&din<64-56>&din<64-24>&din<64-64>&din<64-32>& din<64-39>&din<64-7>&din<64-47>&din<64-15>&din<64-55>&din<64-23>&din<64-63>&din<64-31>& din<64-38>&din<64-6>&din<64-46>&din<64-14>&din<64-54>&din<64-22>&din<64-62>&din<64-30>& din<64-37>&din<64-5>&din<64-45>&din<64-13>&din<64-53>&din<64-21>&din<64-61>&din<64-29>& din<64-36>&din<64-4>&din<64-44>&din<64-12>&din<64-52>&din<64-20>&din<64-60>&din<64-28>& din<64-35>&din<64-3>&din<64-43>&din<64-11>&din<64-51>&din<64-19>&din<64-59>&din<64-27>& din<64-34>&din<64-2>&din<64-42>&din<64-10>&din<64-50>&din<64-18>&din<64-58>&din<64-26>& din<64-33>&din<64-1>&din<64-41>&din<64-9>&din<64-49>&din<64-17>&din<64-57>&din<64-25>; returnval; enddes_fp; -------------------------------------------------------- --Keypermutation,convertsa64bitkeyintoa56bitkey,ignoringparity functiondes_kp std_logic_vector<63downto0>> returnstd_logic_vectoris variableval: std_logic_vector<55downto0>; begin val: =din<64-57>&din<64-49>&din<64-41>&din<64-33>&din<64-25>&din<64-17>&din<64-9>&din<64-1>& din<64-58>&din<64-50>&din<64-42>&din<64-34>&din<64-26>&din<64-18>&din<64-10>&din<64-2>& din<64-59>&din<64-51>&din<64-43>&din<64-35>&din<64-27>&din<64-19>&din<64-11>&din<64-3>& din<64-60>&din<64-52>&din<64-44>&din<64-36>& din<64-63>&din<64-55>&din<64-47>&din<64-39>&din<64-31>&din<64-23>&din<64-15>&din<64-7>& din<64-62>&din<64-54>&din<64-46>&din<64-38>&din<64-30>&din<64-22>&din<64-14>&din<64-6>& din<64-61>&din<64-53>&din<64-45>&din<64-37>&din<64-29>&din<64-21>&din<64-13>&din<64-5>& din<64-28>&din<64-20>&din<64-12>&din<64-4>; returnval; enddes_kp; -------------------------------------------------------- --pressionPermutation,convertsa56bitkeyintoa48bits. functiondes_cp std_logic_vector<55downto0>> returnstd_logic_vectoris variableval: std_logic_vector<47downto0>; begin val: =din<56-14>&din<56-17>&din<56-11>&din<56-24>&din<56-1>&din<56-5>& din<56-3>&din<56-28>&din<56-15>&din<56-6>&din<56-21>&din<56-10>& din<56-23>&din<56-19>&din<56-12>&din<56-4>&din<56-26>&din<56-8>& din<56-16>&din<56-7>&din<56-27>&din<56-20>&din<56-13>&din<56-2>& din<56-41>&din<56-52>&din<56-31>&din<56-37>&din<56-47>&din<56-55>& din<56-30>&din<56-40>&din<56-51>&din<56-45>&din<56-33>&din<56-48>& din<56-44>&din<56-49>&din<56-39>&din<56-56>&din<56-34>&din<56-53>& din<56-46>&din<56-42>&din<56-50>&din<56-36>&din<56-29>&din<56-32>; returnval; enddes_cp; -------------------------------------------------------- --Expansionpermutation functiondes_ep std_logic_vector<31downto0>> returnstd_logic_vectoris variableval: std_logic_vector<47downto0>; begin val: =din<32-32>&din<32-1>&din<32-2>&din<32-3>&din<32-4>&din<32-5>& din<32-4>&din<32-5>&din<32-6>&din<32-7>&din<32-8>&din<32-9>& din<32-8>&din<32-9>&din<32-10>&din<32-11>&din<32-12>&din<32-13>& din<32-12>&din<32-13>&din<32-14>&din<32-15>&din<32-16>&din<32-17>& din<32-16>&din<32-17>&din<32-18>&din<32-19>&din<32-20>&din<32-21>& din<32-20>&din<32-21>&din<32-22>&din<32-23>&din<32-24>&din<32-25>& din<32-24>&din<32-25>&din<32-26>&din<32-27>&din<32-28>&din<32-29>& din<32-28>&din<32-29>&din<32-30>&din<32-31>&din<32-32>&din<32-1>; returnval; enddes_ep; -------------------------------------------------------- --S-BoxSubstitution,48bitsin,32bitsout. functiondes_sbox std_logic_vector<47downto0>> returnstd_logic_vectoris variableval: std_logic_vector<31downto0>; begin --SBOX8 casedin<5downto0>is when"000000"=>val<3downto0>: ="1101";when"000001"=>val<3downto0>: ="0001"; when"000010"=>val<3downto0>: ="0010";when"000011"=>val<3downto0>: ="1111"; when"000100"=>val<3downto0>: ="1000";when"000101"=>val<3downto0>: ="1101"; when"000110"=>val<3downto0>: ="0100";when"000111"=>val<3downto0>: ="1000"; when"001000"=>val<3downto0>: ="0110";when"001001"=>val<3downto0>: ="1010"; when"001010"=>val<3downto0>: ="1111";when"001011"=>val<3downto0>: ="0011"; when"001100"=>val<3downto0>: ="1011";when"001101"=>val<3downto0>: ="0111"; when"001110"=>val<3downto0>: ="0001";when"001111"=>val<3downto0>: ="0100"; when"010000"=>val<3downto0>: ="1010";when"010001"=>val<3downto0>: ="1100"; when"010010"=>val<3downto0>: ="1001";when"010011"=>val<3downto0>: ="0101"; when"010100"=>val<3downto0>: ="0011";when"010101"=>val<3downto0>: ="0110"; when"010110"=>val<3downto0>: ="1110";when"010111"=>val<3downto0>: ="1011"; when"011000"=>val<3downto0>: ="0101";when"011001"=>val<3downto0>: ="0000"; when"011010"=>val<3downto0>: ="0000";when"011011"=>val<3downto0>: ="1110"; when"011100"=>val<3downto0>: ="1100";when"011101"=>val<3downto0>: ="1001"; when"011110"=>val<3downto0>: ="0111";when"011111"=>val<3downto0>: ="0010"; when"100000"=>val<3downto0>: ="0111";when"100001"=>val<3downto0>: ="0010"; when"100010"=>val<3downto0>: ="1011";when"100011"=>val<3downto0>: ="0001"; when"100100"=>val<3downto0>: ="0100";when"100101"=>val<3downto0>: ="1110"; when"100110"=>val<3downto0>: ="0001";when"100111"=>val<3downto0>: ="0111"; when"101000"=>val<3downto0>: ="1001";when"101001"=>val<3downto0>: ="0100"; when"101010"=>val<3downto0>: ="1100";when"101011"=>val<3downto0>: ="1010"; when"101100"=>val<3downto0>: ="1110";when"101101"=>val<3downto0>: ="1000"; when"101110"=>val<3downto0>: ="0010";when"101111"=>val<3downto0>: ="1101"; when"110000"=>val<3downto0>: ="0000";when"110001"=>val<3downto0>: ="1111"; when"110010"=>val<3downto0>: ="0110";when"110011"=>val<3downto0>: ="1100"; when"110100"=>val<3downto0>: ="1010";when"110101"=>val<3downto0>: ="1001"; when"110110"=>val<3downto0>: ="1101";when"110111"=>val<3downto0>: ="0000"; when"111000"=>val<3downto0>: ="1111";when"111001"=>val<3downto0>
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- DES 算法 使用 vhdl 硬件 语言 实现