EDA 作业.docx
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- 上传时间:2023-05-28
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- 页数:29
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EDA 作业.docx
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EDA作业
EDA作业
7-5:
LIBRARYieee;
USEieee.std_logic_1164.all;
LIBRARYaltera_mf;
USEaltera_mf.altera_mf_compontents.all;
ENTITYlpm_rom0IS
PORT
(
address:
INSTD_LOGIC_VECTOR(5DOWNTO0);
inclock:
INSTD_LOGIC;
q:
OUTSTD_LOGIC_VECTOR(7DOWNTO0)
);
ENDlpm_rom0;
ARCHITECTURESYNOFlpm_rom0IS
SIGNALsub_wire0:
STD_LOGIC_VECTOR(7DOWNTO0);
COMPONENTaltsyncram
GENERIC(
address_aclr_a:
STRING;
init_file:
STRING;
intended_device_family:
STRING;
lpm_hint:
STRING;
lpm_type:
STRING;
numwords_a:
NATURAL;
operation_mode:
STRING;
outdata_aclr_a:
STRING;
outdata_reg_a:
STRING;
widthad_a:
NATURAL;
width_a:
NATURAL;
width_byteena_a:
NATURAL
);
PORT(
clock0:
INSTD_LOGIC;
address_a:
INSTD_LOGIC_VECTOR(5DOWNTO0);
q_a:
OUTSTD_LOGIC_VECTOR(7DOWNTO0)
);
ENDCOMPONENT;
BEGIN
q<=sub_wire0(7DOWNTO0);
altsyncram_component:
altsyncram
GENERICMAP(
address_aclr_a=>"NONE",
init_file=>"romd.mif",
intended_device_family=>"Cyclone",
lpm_hint=>"ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=ROM0",
lpm_type=>"altsyncram",
numwords_a=>64,
operation_mode=>"ROM",
outdata_aclr_a=>"NONE",
outdata_reg_a=>"UNREGISTERED",
widthad_a=>6,
width_a=>8,
width_byteena_a=>1
)
PORTMAP(
clock0=>inclock,
address_a=>address,
q_a=>sub_wire0
);
ENDSYN;
LIBRARYIEEE;--正弦信号发生器源文件
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYSINGTIS
PORT(CLK:
INSTD_LOGIC;--信号源时钟
DOUT:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));--8位波形数据输出
END;
ARCHITECTUREDACCOFSINGTIS
COMPONENTlpm_rom0--调用波形数据存储器LPM_ROM文件:
data_rom.vhd声明
PORT(address:
INSTD_LOGIC_VECTOR(5DOWNTO0);--6位地址信号
inclock:
INSTD_LOGIC;--地址锁存时钟
q:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDCOMPONENT;
SIGNALQ1:
STD_LOGIC_VECTOR(5DOWNTO0);--设定内部节点作为地址计数器
BEGIN
PROCESS(CLK)--LPM_ROM地址发生器进程
BEGIN
IFCLK'EVENTANDCLK='1'THENQ1<=Q1+1;--Q1作为地址发生器计数器
ENDIF;
ENDPROCESS;
u1:
lpm_rom0PORTMAP(address=>Q1,q=>DOUT,inclock=>CLK);--例化
END;
其RTL电路图如下:
仿真波形如下
SignalTapII数据窗的实时信号图形如下:
7-2实验与设计:
测频控制程序如下:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYFTCTRLIS
PORT(CLKK:
INSTD_LOGIC;
CNT_EN:
OUTSTD_LOGIC;
RST_CNT:
OUTSTD_LOGIC;
Load:
OUTSTD_LOGIC);
ENDFTCTRL;
ARCHITECTUREbehavOFFTCTRLIS
SIGNALDiv2CLK:
STD_LOGIC;
BEGIN
PROCESS(CLKK)
BEGIN
IFCLKK'EVENTANDCLKK='1'THENDiv2CLK<=NOTDiv2CLK;
ENDIF;
ENDPROCESS;
PROCESS(CLKK,Div2CLK)
BEGIN
IFCLKK='0'ANDDiv2CLK='0'THENRST_CNT<='1';
ELSERST_CNT<='0';
ENDIF;
ENDPROCESS;
Load<=NOTDiv2CLK;
CNT_EN<=Div2CLK;
ENDbehav;
其RTL电路图如下;
其工作时序如下:
32位计数器程序如下:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCOUNTER32BIS
PORT(FIN:
INSTD_LOGIC;
CLR:
INSTD_LOGIC;
ENABL:
INSTD_LOGIC;
DOUT:
OUTSTD_LOGIC_VECTOR(31DOWNTO0));
ENDCOUNTER32B;
ARCHITECTUREbehavOFCOUNTER32BIS
SIGNALCQI:
STD_LOGIC_VECTOR(31DOWNTO0);
BEGIN
PROCESS(FIN,CLR,ENABL)
BEGIN
IFCLR='1'THENCQI<=(OTHERS=>'0');
ELSIFFIN'EVENTANDFIN='1'THEN
IFENABL='1'THENCQI<=CQI+1;
ENDIF;
ENDIF;
ENDPROCESS;
DOUT<=CQI;
ENDbehav;
其RTL电路图如下:
32位锁存器程序如下:
其RTL电路图如下:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYREG32BIS
PORT(LK:
INSTD_LOGIC;
DIN:
INSTD_LOGIC_VECTOR(31DOWNTO0);
DOUT:
OUTSTD_LOGIC_VECTOR(31DOWNTO0));
ENDREG32B;
ARCHITECTUREbehavOFREG32BIS
BEGIN
PROCESS(LK,DIN)
BEGIN
IFLK'EVENTANDLK='1'THENDOUT<=DIN;
ENDIF;
ENDPROCESS;
ENDbehav;
RTL电路如下:
8位16进制频率计顶层文件程序如下:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYFREQTESTIS
PORT(CLK1HZ:
INSTD_LOGIC;
FSIN:
INSTD_LOGIC;
DOUT:
OUTSTD_LOGIC_VECTOR(31DOWNTO0));
ENDFREQTEST;
ARCHITECTUREstrucOFFREQTESTIS
COMPONENTFTCTRL
PORT(CLKK:
INSTD_LOGIC;
CNT_EN:
OUTSTD_LOGIC;
RST_CNT:
OUTSTD_LOGIC;
Load:
OUTSTD_LOGIC);
ENDCOMPONENT;
COMPONENTCOUNTER32B
PORT(FIN:
INSTD_LOGIC;
CLR:
INSTD_LOGIC;
ENABL:
INSTD_LOGIC;
DOUT:
OUTSTD_LOGIC_VECTOR(31DOWNTO0));
ENDCOMPONENT;
COMPONENTREG32B
PORT(LK:
INSTD_LOGIC;
DIN:
INSTD_LOGIC_VECTOR(31DOWNTO0);
DOUT:
OUTSTD_LOGIC_VECTOR(31DOWNTO0));
ENDCOMPONENT;
SIGNALTSTEN1:
STD_LOGIC;
SIGNALCLR_CNT1:
STD_LOGIC;
SIGNALLoad1:
STD_LOGIC;
SIGNALDTO1:
STD_LOGIC_VECTOR(31DOWNTO0);
SIGNALCARRY_OUT1:
STD_LOGIC_VECTOR(6DOWNTO0);
BEGIN
U1:
FTCTRLPORTMAP(CLKK=>CLK1HZ,CNT_EN=>TSTEN1,RST_CNT=>CLR_CNT1,Load=>Load1);
U2:
REG32BPORTMAP(LK=>Load1,DIN=>DTO1,DOUT=>DOUT);
U3:
COUNTER32BPORTMAP(FIN=>FSIN,CLR=>CLR_CNT1,ENABL=>TSTEN1,DOUT=>DTO1);
ENDstruc;
其RTL电路图如下:
其控制时序如下:
8-3:
该状态机为mealy型有限状态机。
程序如下:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYSCHKIS
PORT(DIN,CLK,CLR:
INSTD_LOGIC;
AB:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDSCHK;
ARCHITECTUREbehavOFSCHKIS
SIGNALQ:
INTEGERRANGE0TO8;
SIGNALD:
STD_LOGIC_VECTOR(7DOWNTO0);
BEGIN
D<="11100101";
PROCESS(CLK,CLR)
BEGIN
IFCLR='1'THENQ<=0;
ELSIFCLK'EVENTANDCLK='1'THEN
CASEQIS
WHEN0=>IFDIN=D(7)THENQ<=1;ELSEQ<=0;ENDIF;
WHEN1=>IFDIN=D(6)THENQ<=2;ELSEQ<=0;ENDIF;
WHEN2=>IFDIN=D(5)THENQ<=3;ELSEQ<=0;ENDIF;
WHEN3=>IFDIN=D(4)THENQ<=4;ELSEQ<=0;ENDIF;
WHEN4=>IFDIN=D(3)THENQ<=5;ELSEQ<=0;ENDIF;
WHEN5=>IFDIN=D
(2)THENQ<=6;ELSEQ<=0;ENDIF;
WHEN6=>IFDIN=D
(1)THENQ<=7;ELSEQ<=0;ENDIF;
WHEN7=>IFDIN=D(0)THENQ<=8;ELSEQ<=0;ENDIF;
WHENOTHERS=>Q<=0;
ENDCASE;
ENDIF;
ENDPROCESS;
PROCESS(Q)
BEGIN
IFQ=8THENAB<="1010";
ELSEAB<="1011";
ENDIF;
ENDPROCESS;
ENDbehav;
其RTL电路图如下;
时序仿真:
因为给定的DIN序列中与预赋值有所不同,故显示1011.
该程序无状态机。
(designhasnostatemachine)
实验与设计8_3:
用LPM_RAM调出程序如下:
LIBRARYieee;
USEieee.std_logic_1164.all;
LIBRARYaltera_mf;
USEaltera_mf.all;
ENTITYRAM8BIS
PORT
(
address:
INSTD_LOGIC_VECTOR(7DOWNTO0);
clock:
INSTD_LOGIC;
data:
INSTD_LOGIC_VECTOR(7DOWNTO0);
wren:
INSTD_LOGIC;
q:
OUTSTD_LOGIC_VECTOR(7DOWNTO0)
);
ENDRAM8B;
ARCHITECTURESYNOFram8bIS
SIGNALsub_wire0:
STD_LOGIC_VECTOR(7DOWNTO0);
COMPONENTaltsyncram
GENERIC(
address_aclr_a:
STRING;
indata_aclr_a:
STRING;
intended_device_family:
STRING;
lpm_hint:
STRING;
lpm_type:
STRING;
numwords_a:
NATURAL;
operation_mode:
STRING;
outdata_aclr_a:
STRING;
outdata_reg_a:
STRING;
power_up_uninitialized:
STRING;
widthad_a:
NATURAL;
width_a:
NATURAL;
width_byteena_a:
NATURAL;
wrcontrol_aclr_a:
STRING
);
PORT(
wren_a:
INSTD_LOGIC;
clock0:
INSTD_LOGIC;
address_a:
INSTD_LOGIC_VECTOR(7DOWNTO0);
q_a:
OUTSTD_LOGIC_VECTOR(7DOWNTO0);
data_a:
INSTD_LOGIC_VECTOR(7DOWNTO0)
);
ENDCOMPONENT;
BEGIN
q<=sub_wire0(7DOWNTO0);
altsyncram_component:
altsyncram
GENERICMAP(
address_aclr_a=>"NONE",
indata_aclr_a=>"NONE",
intended_device_family=>"Cyclone",
lpm_hint=>"ENABLE_RUNTIME_MOD=NO",
lpm_type=>"altsyncram",
numwords_a=>256,
operation_mode=>"SINGLE_PORT",
outdata_aclr_a=>"NONE",
outdata_reg_a=>"CLOCK0",
power_up_uninitialized=>"FALSE",
widthad_a=>8,
width_a=>8,
width_byteena_a=>1,
wrcontrol_aclr_a=>"NONE"
)
PORTMAP(
wren_a=>wren,
clock0=>clock,
address_a=>address,
data_a=>data,
q_a=>sub_wire0
);
ENDSYN;
元件ADCINT的程序如下:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYADCINTIS
PORT(D:
INSTD_LOGIC_VECTOR(7DOWNTO0);--来自0809转换好的8位数据
CLK:
INSTD_LOGIC;--状态机工作时钟
EOC:
INSTD_LOGIC;--转换状态指示,低电平表示正在转换
ALE:
OUTSTD_LOGIC;--8个模拟信号通道地址锁存信号
START:
OUTSTD_LOGIC;--转换开始信号
OE:
OUTSTD_LOGIC;--数据输出3态控制信号
ADDA:
OUTSTD_LOGIC;--信号通道最低位控制信号
LOCK0:
OUTSTD_LOGIC;--观察数据锁存时钟
Q:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));--8位数据输出
ENDADCINT;
ARCHITECTUREbehavOFADCINTIS
TYPEstatesIS(st0,st1,st2,st3,st4);--定义各状态子类型
SIGNALcurrent_state,next_state:
states:
=st0;
SIGNALREGL:
STD_LOGIC_VECTOR(7DOWNTO0);
SIGNALLOCK:
STD_LOGIC;--转换后数据输出锁存时钟信号
BEGIN
ADDA<='1';--当ADDA<='0',模拟信号进入通道IN0;当ADDA<='1',则进入通道IN1
Q<=REGL;LOCK0<=LOCK;
COM:
PROCESS(current_state,EOC)BEGIN--规定各状态转换方式
CASEcurrent_stateIS
WHENst0=>ALE<='0';START<='0';LOCK<='0';OE<='0';next_state<=st1;--0809初始化
WHENst1=>ALE<='1';START<='1';LOCK<='0';OE<='0';next_state<=st2;--启动采样
WHENst2=>ALE<='0';START<='0';LOCK<='0';OE<='0';
IF(EOC='1')THENnext_state<=st3;--EOC=1表明转换结束
ELSEnext_state<=st2;ENDIF;--转换未结束,继续等待
WHENst3=>ALE<='0';START<='0';LOCK<='0';OE<='1';next_state<=st4;--开启OE,输出转换好的数据
WHENst4=>ALE<='0';START<='0';LOCK<='1';OE<='1';next_state<=st0;
WHENOTHERS=>next_state<=st0;
ENDCASE;
ENDPROCESSCOM;
REG:
PROCESS(CLK)
BEGIN
IF(CLK'EVENTANDCLK='1')THENcurrent_state<=next_state;ENDIF;
ENDPROCESSREG;--由信号current_state将当前状态值带出此进程:
REG
LATCH1:
PROCESS(LOCK)--此进程中,在LOCK的上升沿,将转换好的数据锁入
BEGIN
IFLOCK='1'ANDLOCK'EVENTTHENREGL<=D;ENDIF;
ENDPROCESSLATCH1;
ENDbehav;
元件CINT10B的程序如下:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCNT10BIS
PORT(LOCK0,CLR:
INSTD_LOGIC;
CLK:
INSTD_LOGIC;
WE:
INSTD_LOGIC;
DOUT:
OUTSTD_LOGIC_VECTOR(8DOWNTO0);
CLKOUT:
OUTSTD_LOGIC);
ENDCNT10B;
ARCHITECTUREbehavOFCNT10BIS
SIGNALCQI:
STD_LOGIC_VECTOR(8DOWNTO0);
SIGNALCLK0:
STD_LOGIC;
BEGIN
CLK0<=LOCK0WHENWE='1'ELSE
CLK;
PROCESS(CLK0,CLR,CQI)
BEGIN
IFCLR='1'THENCQI<="000000000";
ELSIFCLK0'EVENTANDCLK0='1'THENCQI<=CQI+1;ENDIF;
ENDPROCESS;
DOUT<=CQI;CLKOUT<=CLK0;
ENDbehav;
AD
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