数字电路逻辑设计FPGA 交通灯设计.docx
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数字电路逻辑设计FPGA 交通灯设计.docx
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数字电路逻辑设计FPGA交通灯设计
北京联合大学
数电实验报告
姓 名:
李冬冬
学 号:
2010080303114
学院:
信息学院
专业:
电子信息工程
指导教师:
杨静
2012年12月28日
课程设计—交通灯控制系统设计
第一章交通灯控制系统工程设计要求
1、基础功能要求
设计一个简单自控控制的交通灯控制系统。
具体要求,在道路十字路口的两个方向各设一组红黄绿指示灯,显示顺序为,其中一个方向是绿灯、黄灯、红灯是,另外一个方向是红灯、绿灯、黄灯;设置一组数码管,以倒计时的方式显示允许通过或禁止通过实践,其中绿灯、黄灯、红灯的持续时间分别是20s、5s、25s。
交通灯基础功能状态表如下表1-1.1
工作状态
南北方向
东西方向
S0
绿灯亮
红灯亮
S1
黄灯亮
红灯亮
S2
红灯亮
绿灯亮
S3
红灯亮
黄灯亮
表1-1.1交通灯点亮状态表
第二章基础功能模块电路设计
1、南北方向控制模块设计
南北方向控制模块(cona)设计的要求是:
初始状态设置为绿灯亮。
数码管倒计时从19秒到0秒,然后依次是黄灯亮,持续时间5秒,红灯亮,持续时间258秒。
南北方向控制模块设计的VHDL程序如下:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityconais
port(rst,clk:
instd_logic;
r,g,y:
outstd_logic;
timh,timl:
outstd_logic_vector(3downto0));
endcona;
architecturecom_arcofconais
typergyis(green,yellow,red);
begin
process(clk)
variablea:
std_logic;
variableth,tl:
std_logic_vector(3downto0);
variablestate:
rgy;
begin
ifrst='1'then
state:
=green;
a:
='0';
elsifclk'eventandclk='1'then
casestateis
whengreen=>ifa='0'then
th:
="0001";tl:
="1001";
a:
='1';
g<='1';r<='0';y<='0';
else
ifnot(th="0000"andtl="0001")
then
iftl="0000"then
tl:
="1001";th:
=th-1;
else
tl:
=tl-1;
endif;
else
th:
="0000";tl:
="0000";
a:
='0';
state:
=yellow;
endif;
endif;
whenyellow=>ifa='0'then
th:
="0000";tl:
="0100";
a:
='1';
g<='0';r<='0';y<='1';
else
ifnot(tl="0001")then
tl:
=tl-1;
else
tl:
="0000";
a:
='0';
state:
=red;
endif;
endif;
whenred=>ifa='0'then
th:
="0010";tl:
="0100";
a:
='1';
g<='0';r<='1';y<='0';
else
ifnot(th="0000"andtl="0001")then
iftl="0000"then
tl:
="1001";th:
=th-1;
else
tl:
=tl-1;
endif;
else
th:
="0000";tl:
="0000";
a:
='0';
state:
=green;
endif;
endif;
whenothers=>state:
=green;
a:
='0';
endcase;
endif;
timh<=th;
timl<=tl;
endprocess;
endcom_arc;
2、东西方向控制模块设计
东西方向控制模块(conb)设计的要求是:
初始状态设置为红灯亮。
数码管倒计时从25到0,然后依次是绿灯亮,持续时间20秒,最后是黄灯亮持续时间5秒。
程序基本与南北方向模块相同。
初始状态有所调整且设计顺序不同。
东西方向控制模块设计的VHDL程序如下:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityconbis
port(rst,clk:
instd_logic;
r,g,y:
outstd_logic;
timh,timl:
outstd_logic_vector(3downto0));
endconb;
architecturecom_arcofconbis
typergyis(green,yellow,red);
begin
process(clk)
variablea:
std_logic;
variableth,tl:
std_logic_vector(3downto0);
variablestate:
rgy;
begin
ifrst='1'then
state:
=red;
a:
='0';
elsifclk'eventandclk='1'then
casestateis
whenred=>ifa='0'then
th:
="0010";tl:
="0100";
a:
='1';
g<='0';r<='1';y<='0';
else
ifnot(th="0000"andtl="0001")
then
iftl="0000"then
tl:
="1001";th:
=th-1;
else
tl:
=tl-1;
endif;
else
th:
="0000";tl:
="0000";
a:
='0';
state:
=green;
endif;
endif;
whengreen=>ifa='0'then
th:
="0001";tl:
="1001";
a:
='1';
g<='1';r<='0';y<='0';
else
ifnot(th="0000"andtl="0001")then
iftl="0000"then
tl:
="1001";th:
=th-1;
else
tl:
=tl-1;
endif;
else
th:
="0000";tl:
="0000";
a:
='0';
state:
=yellow;
endif;
endif;
whenyellow=>ifa='0'then
th:
="0000";tl:
="0100";
a:
='1';
g<='0';r<='0';y<='1';
else
ifnot(tl="0001")then
tl:
=tl-1;
else
tl:
="0000";
a:
='0';
state:
=red;
endif;
endif;
whenothers=>state:
=green;
a:
='0';
endcase;
endif;
timh<=th;
timl<=tl;
endprocess;
endcom_arc;
3.1Hz分频模块设计
LIBRARYieee;
USEieee.std_logic_1164.ALL;
USEieee.std_logic_unsigned.ALL;
ENTITYclk1IS
PORT(clk:
INstd_logic;
clk_1:
OUTstd_logic);
END;
ARCHITECTUREw1OFclk1IS
BEGIN
PROCESS(clk)
VARIABLEq:
std_logic_vector(24DOWNTO0);
BEGIN
IFclk'EVENTANDclk='1'THEN
IFq=9999999THEN
q:
=(OTHERS=>'0');clk_1<='1';
ELSEq:
=q+1;clk_1<='0';
ENDIF;
ENDIF;
ENDPROCESS;
END;
4.500Hz分频模块设计
LIBRARYieee;
USEieee.std_logic_1164.ALL;
USEieee.std_logic_unsigned.ALL;
ENTITYclk500IS
PORT(clk:
INstd_logic;
clk500:
OUTstd_logic);
END;
ARCHITECTUREw1OFclk500IS
BEGIN
PROCESS(clk)
VARIABLEq:
std_logic_vector(15DOWNTO0);
BEGIN
IFclk'EVENTANDclk='1'THEN
IFq=19999THEN
q:
=(OTHERS=>'0');clk500<='1';
ELSEq:
=q+1;clk500<='0';
ENDIF;
ENDIF;
ENDPROCESS;
END;
5.扫描显示模块设计
LIBRARYieee;
USEieee.std_logic_1164.ALL;
USEieee.std_logic_unsigned.ALL;
ENTITYscan_ledIS
PORT(q1,q2,q3,q4:
INstd_logic_vector(3DOWNTO0);
clk0:
INstd_logic;
sg:
OUTstd_logic_vector(6DOWNTO0);
com:
OUTstd_logic_vector(3DOWNTO0));
END;
ARCHITECTUREoneOFscan_ledIS
SIGNALcnt4:
std_logic_vector(1DOWNTO0);
SIGNALa:
std_logic_vector(3DOWNTO0);
BEGIN
p1:
PROCESS(cnt4)
BEGIN
CASEcnt4IS
WHEN"00"=>com<="0001";a<=q1;
WHEN"01"=>com<="0010";a<=q2;
WHEN"10"=>com<="0100";a<=q3;
WHEN"11"=>com<="1000";a<=q4;
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESSp1;
p2:
PROCESS(clk0)
BEGIN
IFclk0'EVENTANDclk0='1'THEN
IFcnt4="11"THENcnt4<="00";
ELSEcnt4<=cnt4+1;
ENDIF;
ENDIF;
ENDPROCESSp2;
p3:
PROCESS(a)
BEGIN
CASEaIS
WHEN"0000"=>sg<="0111111";
WHEN"0001"=>sg<="0000110";
WHEN"0010"=>sg<="1011011";
WHEN"0011"=>sg<="1001111";
WHEN"0100"=>sg<="1100110";
WHEN"0101"=>sg<="1101101";
WHEN"0110"=>sg<="1111101";
WHEN"0111"=>sg<="0000111";
WHEN"1000"=>sg<="1111111";
WHEN"1001"=>sg<="1101111";
WHENOTHERS=>sg<="0000000";
ENDCASE;
ENDPROCESSp3;
END;
6.顶层模块设计
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycontrolis
port(rst,clksys:
instd_logic;
r1,g1,y1:
outstd_logic;
r2,g2,y2:
outstd_logic;
com1:
OUTstd_logic_vector(3DOWNTO0);
sg1:
OUTstd_logic_vector(6DOWNTO0));
end;
architecturem1ofcontrolis
SIGNALclk2:
std_logic;
SIGNALclk3:
std_logic;
SIGNALclk4:
std_logic;
SIGNALs1:
std_logic_vector(3downto0);
SIGNALs2:
std_logic_vector(3downto0);
SIGNALs3:
std_logic_vector(3downto0);
SIGNALs4:
std_logic_vector(3downto0);
componentconais
port(rst1,clkn:
instd_logic;
r,g,y:
outstd_logic;
timh,timl:
outstd_logic_vector(3downto0));
endcomponent;
componentconbis
port(rst2,clkd:
instd_logic;
r,g,y:
outstd_logic;
timh,timl:
outstd_logic_vector(3downto0));
endcomponent;
componentclk1is
PORT(clk:
INstd_logic;
clk_1:
OUTstd_logic);
endcomponent;
componentclk500is
PORT(clk:
INstd_logic;
clk500:
OUTstd_logic);
endcomponent;
componentscan_ledis
PORT(q1,q2,q3,q4:
INstd_logic_vector(3DOWNTO0);
clk0:
INstd_logic;
sg:
OUTstd_logic_vector(6DOWNTO0);
com:
OUTstd_logic_vector(3DOWNTO0));
endcomponent;
begin
u1:
conaportmap(rst1=>rst,clkn=>clk2,r=>r1,g=>g1,y=>y1,timh=>s1,timl=>s2);
u2:
conbportmap(rst2=>rst,clkd=>clk3,r=>r2,g=>g2,y=>y2,timh=>s3,timl=>s4);
u3:
clk1portmap(clk=>clksys,clk_1=>clk2);
u4:
clk1portmap(clk=>clksys,clk_1=>clk3);
u5:
clk500portmap(clk=>clksys,clk500=>clk4);
u6:
scan_ledportmap(q1=>s1,q2=>s2,q3=>s3,q4=>s4,clk0=>clk4,sg=>sg1,com=>com1);
end;
7.系统引脚配置模块设计
set_global_assignment-nameRESERVE_ALL_UNUSED_PINS"ASINPUTTRI-STATED"
set_location_assignmentPIN_59-torst
set_location_assignmentPIN_28-toclksys
set_location_assignmentPIN_113-tor1
set_location_assignmentPIN_105-toy1
set_location_assignmentPIN_101-tog1
set_location_assignmentPIN_88-tog2
set_location_assignmentPIN_86-toy2
set_location_assignmentPIN_84-tor2
set_location_assignmentPIN_76-tocom1[3]
set_location_assignmentPIN_68-tocom1[2]
set_location_assignmentPIN_62-tocom1[1]
set_location_assignmentPIN_60-tocom1[0]
set_location_assignmentPIN_83-tosg1[0]
set_location_assignmentPIN_79-tosg1[1]
set_location_assignmentPIN_77-tosg1[2]
set_location_assignmentPIN_75-tosg1[3]
set_location_assignmentPIN_67-tosg1[4]
set_location_assignmentPIN_65-tosg1[5]
附录
附录1-小组成员与成员分工
2010080303114李冬冬
负责南北模块程序、东西方向控制模块设计、1Hz分频模块设计、500Hz分频模块设计、顶层模块设计、系统引脚配置模块设计的程序编写、调试、连接互调。
附录2-参考资料
[1]王传新——《FPGA设计基础》,高等教育出版社
[2]王毓银、杨静——《数字电路逻辑设计》,高等教育出版社
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