基于FPGA索贝尔边缘检测算子的安全体系.docx
- 文档编号:24299816
- 上传时间:2023-05-26
- 格式:DOCX
- 页数:12
- 大小:605.29KB
基于FPGA索贝尔边缘检测算子的安全体系.docx
《基于FPGA索贝尔边缘检测算子的安全体系.docx》由会员分享,可在线阅读,更多相关《基于FPGA索贝尔边缘检测算子的安全体系.docx(12页珍藏版)》请在冰豆网上搜索。
基于FPGA索贝尔边缘检测算子的安全体系
AnovelFPGA-basedarchitectureforSobeledgedetectionoperator
T.A.ABBASIyandM.U.ABBASI*zyDepartmentofElectronicsandCommunicationEngineering,UniversityPolytechnic,JamiaMilliaIslamia,NewDelhi-110025,IndiazVirageLogicInternational,Sector-57,Noida,UP-201307,India(Received9June2006;infinalform27August2007)AnovelFPGA-basedarchitectureforSobeledgedetectionalgorithmhasbeenproposed.TheSobelalgorithmischosenduetoitspropertyofprovidingadifferencingaswellasnoisesmoothingoperationinthesinglekernel.Thus,noisesensitivityoffirstgradientbasedoperationscanbeavoidedbytheuseofthisalgorithm.Theimplementationofedgedetectionalgorithmsonafieldprogrammablegatearray(FPGA)ismotivatedbythefactthatlargememory
FPGAsarenowavailable,providingaplatformforprocessingrealtimealgorithmsonapplication-specifichardwarewithsubstantiallyhigherperformancethanprogrammabledigitalsignalprocessors(DSPs).Thisarchitecturecanbeusedasabuildingblockofapatternrecognitionsystem,autonomousrobotnavigation,andalsoasasystemforcreatinganimagedazzlingeffectinmultimediagraphics.Thisarchitectureisimplicitlypipelinedtoprovideasystemcapableofoperatingataclockspeedof99.499MHzwhichisasignificantimprovementoverprogrammableDSPsimplementation.
Keywords:
Edgedetectionalgorithms;Firstgradientbasedoperators;Hardware
implementation;Sobeloperators;VLSI
1.Introduction
Edgesareconsideredtobethemostimportantimageattributesthatprovidevaluableinformationforhumanimageperception.Imageedgesoccurinplacesofsignificantintensitychangesontheimage.Therearemanykindsofintensitychangesinanimage.Theusualaimofedgedetectionistolocateedgesbelongingtoboundariesofobjectsofinterest.Recognitionorclassificationofpicturesbydigitalcomputerisgenerallydonebyusingtheinformationcontainedintheedgesbetweendifferentregions.Thishasrecognizededgedetectionasthemostessentialtaskinimageprocessing,patternrecognitionandrobotics.Whilethehumaneyesperformthistaskeasily,thedetectionofedgesonamachineisadifficulttasktoachieve.Consequently,substantialefforthasbeendirectedtowardsthisproblem,resultinginanumberofedgedetectionalgorithms(Jain1989,ChandaandDuttaMajumdar
2001,GonzalezandWoods2002,Bose2004,Pratt2004,Heathetal.2002).However,mostoftheseeffortshavebeenconcentratedonfindingbetteredge
detectionalgorithmsratherthantheirimplementationissues.
Presently,implementationofedgedetectionalgorithmsislimitedtoprogrammabledigitalsignalprocessors(DSPs),whicharespecializedmicrocomputers.Theyarebasedonareducedinstructionsetcomputer(RISC)paradigmwithan
architectureconsistingofatleastonefastarraymultiplier(e.g.16_16-bitto24_24-bitfixedpointor32-bitfloatingpoint),withanextendedword-widthaccumulator.ThedisadvantagewiththeprogrammableDSPsisthatofspeed,astheyhaveafixedarchitecturetomaptherequiredapplication.Nowadays,researchesonprogrammabledevicesmakeitpossibletoimplementedgedetectionalgorithmsonthesedeviceswhosedesignturn-aroundtimevariesfromafewhourstoafewdays.
Duringrecentyears,fieldprogrammablegatearrays(FPGAs)havebecomethedominantformofprogrammablelogic(Jenkins1994,Smith1997,WesteandEshraghian2000,Wakerly2002).Incomparisontopreviousprogrammabledevices
likeprogrammablearraylogic(PAL)andcomplexprogrammablelogicdevices(CPLDs),FPGAscanimplementfarlargerlogicfunctions.FPGAsupports
sufficientlogictoimplementcompletesystemsandsub-systems.FPGAexploitstheincreasingcapacityofintegratedcircuitstoprovidedesignerswithreconfigurablelogicthatcanbeprogrammedonanapplication-specificbasis.Thisdrasticallyincreasesflexibilityinboththedesignprocessandthefinalartifactbypermittingoneboard-leveldesigntoperformmanyfunctions,ortobeupgradedinthefield.FPGAsperformanceissuperiortothatofprogrammableDSPs,astheysupporttheuseof
highlyparallelarchitectures.ThoughthedesigneffortofanFPGAsolutionisgreaterthanthatforaprogrammableDSP,theadoptionofhardwaredescriptionlanguagesandflexiblecorecomponentlibraries(suchasXilinx’scoretools)isreducingthiseffortsignificantly.Moreover,increaseinembeddedmemoryenablesthehighprocessorcountwithoutlimitationsofI/O,lowpackagecountand
flexibilityasthewholearchitecturemaybereprogrammedwithouttheconstraintsoffixedmemorynumber.
Inthispaper,aFPGA-basedimplementationofSobeledgedetectionalgorithmhasbeenproposed.ThechoiceofaSobeledgedetectionoperatorismotivatedbythefactthattheyincorporateboththeedgedetectionandasmoothingoperatortoprovidegoodedgedetectioncapabilityinnoisyconditions.Thedesignisbasedonparallelmoduleswithinternalpipelineoperationinordertospeed-upitsoperation.Applicationstargetedareinhighspeedcomputervision(i.e.morethan100imagespersecond).ThesoftwareplatformusedisXilinxISE7.1ifromXilinxCorporationwithsimulationonModelsimSE5.8csimulatorandsynthesisonLeonardospectrum2004,bothfrommentorGraphicsCorporation.ArchitectureisvalidatedforXC3S1500-5FG320devicefromXilinx’sSpartan3FPGAfamily.
2.AlgorithmofSobeledgedetector
Theedgedetectionalgorithmsarebasicallydividedintotwosteps.Thefirststepof
edgedetectionrequirestheevaluationofderivativesoftheimageintensity.Tocharacterizethetypesofintensitychanges,derivativesofdifferenttypeandordermaybeneeded,possiblyatdifferentscales.TheSobeledgedetectionoperatorisbasedonafirstderivativebasedoperation,showninfigure1.Thealgorithmsoffirstderivativeorfirstdifferencebasedoperatorarethesimplest,thatiswhytheyareselectedforimplementationonthehardwaredevice.
Figure1.OperationoftheSobel-edgedetectionalgorithm
Consideru(p,q)tobethetwodimensionaledgesegment.Itisknownthatorthogonaledgegradientcanbeformedbyrunningdifferentpixelsinhorizontalandverticaldirections.Itisdefinedinmagnitudeformasthesumofthemagnitudesof
verticalandhorizontalgradient
Inmachinevisionaswellasinmostnumericalproblems,thedataisnoisy.
Noiseinthephototransductionprocessisultimatelyunavoidable.Sensornoisearises,atleastinpart,fromquantumfluctuationsinthenumberofabsorbedphotonspersensorandunittime.Thisrepresentsafundamentallimitationforrealtimeimagery.ItiscriticallyimportantthattheresultsofnumericaloperationsperformedonthedataFigure1.OperationoftheSobel-edgedetectionalgorithm.
FPGA-basedarchitectureforSobeloperator891
arenottoosensitivetonoise.Itisalsowellknownthatdifferentiationisnotrobustagainstnoise.Evenasmallamountofnoisemaydisruptdifferentiation.Considerafunctionf(t)and^fetT_fetTt_sin!
t.f(t)maybecloseto^fetT,butf0(t)maybequite
differentfrom^f0etTif!
islarge.Thisshowsthatgradientbasedoperationsarehighlysusceptibletonoiseandrequirenoisesmoothingbeforefurtherprocessing.Sobeloperationsaddressthisproblembyincorporatingdifferencingandsmoothingoperationinthesinglekernel
Theweightsusedinthehorizontalandverticalneighbourhoodareusedfornoisesmoothingbygivingmoreimportancetoneighbourhoodpixels.Thereasonforchoosingthe3_3neighbourhoodistomaketheoperatorlesssensitivetonoise.Thisoperatorperformsdifferencinginonedimensionandweightedspatialaveraginginanotherforgettingasmoothededge.
Thefinalstepofthisoperationistofilterouttheedgepixelsfromnon-edgepixelsbycomparingitwithapredeterminedthreshold.Thechoiceofthresholdistotallyapplicationdependent.
3.Proposedarchitecture
Theproposedarchitectureisshowninfigure2.Extraflip-flopsareusedtospeed-uptheprocess.Theseareshownbylightboxeswithedge-triggeredbehaviour.Theinputscomingtotheaddressgeneratorschemeare8-bitpixelvaluesandawrite
enablebit.The3_3kerneloperationresultsinreductionofimagedimensionfrom
Figure2.ProposedarchitectureforSobeledgedetectionoperator
[M,N]to[M-2,N-2].So,theimagematrixhadtobepaddedfirsttoincreaseitssizefrom[512,512]to[514,514].Toaccommodatethisimagematrix,amemoryof514_38byteshasbeendeclared.Whenthewriteenablesignaloftheaddressgeneratorblockisasserted,writingtothismemoryhasresultedinthestorageof38rowsand514columnsoftheimage.Whenthreerowsarecompletelyfilled,thereadenablebitisassertedwhichstartstheprocessingofpixelvalues.After38rowsoftheimagearecompletelyfilled,theremainingrowscanbefilled.Inthesameway,thewholeimageiswritefirstandthenreadtoprocess.Duringthereadingprocess,the3_3kernelmovesinzigzagpatternwhichgivestheoutputsoftheblockaseightpixelvalueswhichareassignedfrommemoryas:
Thepointeriincrementsfrom0to18501.Anotherpointerkisdeclaredwhichincrementsoneachshiftofthekernelinhorizontaldirection.
Afterprocessingof512pixels,thispointerkshiftsthe3_3kerneldownwardbyonerow.Itssyntaxis:
always@(posedgeclock)
Theoutputofthedecoderistwelvepixelvalueswhichthengointodifferentweighingblockswheretheweightsof1,2,1and_1,_2,_1areappendedtothem.Generally,divisionisdifficulttoachieveondigitalhardware,soitisadvantageoustouseassmalladivisionaspossible.Wecaneasilyimplementthe
divideby2anddivideby4processeson
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- 基于 FPGA 贝尔 边缘 检测 算子 安全 体系
![提示](https://static.bdocx.com/images/bang_tan.gif)