STM32F407VGT6芯片管脚功能定义.docx
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- 上传时间:2023-05-25
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STM32F407VGT6芯片管脚功能定义.docx
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STM32F407VGT6芯片管脚功能定义
STM32F407VGT6芯片管脚功能定义
LT
新定义
19
VDD
20
VSSA
21
VREF+
22
VDDA
23
PA0-WKUP
(PA0)
USART2_CTS/UART4_TX/
ETH_MII_CRS/
TIM2_CH1_ETR/
TIM5_CH1/TIM8_ETR/
EVENTOUT
24
PA1
USART2_RTS/
UART4_RX/
ETH_RMII_REF_CLK/
ETH_MII_RX_CLK/
TIM5_CH2/TIMM2_CH2/
EVENTOUT
25
PA2
USART2_TX/TIM5_CH3/
TIM9_CH1/TIM2_CH3/
ETH_MDIO/EVENTOUT
26
PA3
USART2_RX/TIM5_CH4/
TIM9_CH2/TIM2_CH4/
OTG_HS_ULPI_D0/
ETH_MII_COL/
EVENTOUT
27
VSS
28
VDD
29
PA4
SPI1_NSS/SPI3_NSS/
USART2_CK/
DCMI_HSYNC/
OTG_HS_SOF/I2S3_WS/
EVENTOUT
30
PA5
SPI1_SCK/
OTG_HS_ULPI_CK/
TIM2_CH1_ETR/
TIM8_CHIN/EVENTOUT
31
PA6
SPI1_MISO/
TIM8_BKIN/TIM13_CH1/
DCMI_PIXCLK/TIM3_CH1
/TIM1_BKIN/EVENTOUT
32
PA7
SPI1_MOSI/TIM8_CH1N/
TIM14_CH1/TIM3_CH2/
ETH_MII_RX_DV/
TIM1_CH1N/
RMII_CRS_DV/
EVENTOUT
33
PC4
ETH_RMII_RX_D0/
ETH_MII_RX_D0/
EVENTOUT
34
PC5
ETH_RMII_RX_D1/
ETH_MII_RX_D1/
EVENTOUT
35
PB0
TIM3_CH3/TIM8_CH2N/
OTG_HS_ULPI_D1/
ETH_MII_RXD2/
TIM1_CH2N/EVENTOUT
36
PB1
TIM3_CH4/TIM8_CH3N/
OTG_HS_ULPI_D2/
ETH_MII_RXD3/
OTG_HS_INTN/
TIM1_CH3N/EVENTOUT
37
PB2-BOOT1
(PB2)
EVENTOUT
38
PE7
FSMC_D4/TIM1_ETR/
EVENTOUT
39
PE8
FSMC_D5/TIM1_CH1N/
EVENTOUT
40
PE9
FSMC_D6/TIM1_CH1/
EVENTOUT
41
PE10
FSMC_D7/TIM1_CH2N/
EVENTOUT
42
PE11
FSMC_D8/TIM1_CH2/EVENTOUT
43
PE12
FSMC_D9/TIM1_CH3N/
EVENTOUT
44
PE13
FSMC_D10/TIM1_CH3/
EVENTOUT
45
PE14
FSMC_D11/TIM1_CH4/
EVENTOUT
46
PE15
FSMC_D12/TIM1_BKIN/
EVENTOUT
47
PB10
SPI2_SCK/I2S2_CK/
I2C2_SCL/USART3_TX/
OTG_HS_ULPI_D3/
ETH_MII_RX_ER/
TIM2_CH3/EVENTOUT
48
PB11
I2C2_SDA/USART3_RX/
OTG_HS_ULPI_D4/
ETH_RMII_TX_EN/
ETH_MII_TX_EN/
TIM2_CH4/EVENTOUT
49
VCAP_1
50
VDD
51
PB12
SPI2_NSS/I2S2_WS/
I2C2_SMBA/
USART3_CK/TIM1_BKIN/
CAN2_RX/
OTG_HS_ULPI_D5/
ETH_RMII_TXD0/
ETH_MII_TXD0/
OTG_HS_ID/EVENTOUT
52
PB13
SPI2_SCK/I2S2_CK/
USART3_CTS/
TIM1_CH1N/CAN2_TX/
OTG_HS_ULPI_D6/
ETH_RMII_TXD1/
ETH_MII_TXD1/
EVENTOUT
53
PB14
SPI2_MISO/TIM1_CH2N/
TIM12_CH1/
OTG_HS_DM/
USART3_RTS/
TIM8_CH2N/I2S2ext_SD/
EVENTOUT
54
PB15
SPI2_MOSI/I2S2_SD/
TIM1_CH3N/TIM8_CH3N
/TIM12_CH2/
OTG_HS_DP/EVENTOUT
55
PD8
FSMC_D13/USART3_TX/
EVENTOUT
56
PD9
FSMC_D14/USART3_RX/
EVENTOUT
57
PD10
FSMC_D15/USART3_CK/
EVENTOUT
58
PD11
FSMC_CLE/
FSMC_A16/USART3_CTS/
EVENTOUT
59
PD12
FSMC_ALE/
FSMC_A17/TIM4_CH1/
USART3_RTS/
EVENTOUT
60
PD13
FSMC_A18/TIM4_CH2/
EVENTOUT
61
PD14
FSMC_D0/TIM4_CH3/
EVENTOUT/EVENTOUT
62
PD15
FSMC_D1/TIM4_CH4/
EVENTOUT
63
PC6
I2S2_MCK/
TIM8_CH1/SDIO_D6/
USART6_TX/
DCMI_D0/TIM3_CH1/
EVENTOUT
64
PC7
I2S3_MCK/
TIM8_CH2/SDIO_D7/
USART6_RX/
DCMI_D1/TIM3_CH2/
EVENTOUT
65
PC8
TIM8_CH3/SDIO_D0
/TIM3_CH3/USART6_CK/
DCMI_D2/EVENTOUT
66
PC9
I2S_CKIN/MCO2/
TIM8_CH4/SDIO_D1/
/I2C3_SDA/DCMI_D3/
TIM3_CH4/EVENTOUT
67
PA8
MCO1/USART1_CK/
TIM1_CH1/I2C3_SCL/
OTG_FS_SOF/
EVENTOUT
68
PA9
USART1_TX/TIM1_CH2/
I2C3_SMBA/DCMI_D0/
EVENTOUT
69
PA10
USART1_RX/TIM1_CH3/
OTG_FS_ID/DCMI_D1/
EVENTOUT
70
PA11
USART1_CTS/CAN1_RX
/TIM1_CH4/
OTG_FS_DM/EVENTOUT
71
PA12
USART1_RTS/CAN1_TX/
TIM1_ETR/OTG_FS_DP/
EVENTOUT
72
PA1
JTMS-SWDIO)
JTMS-SWDIO/EVENTOUT
73
VCAP_2
74
VSS
75
VDD
76
PA14
(JTCK-SWCLK)
JTCK-SWCLK/EVENTOUT
77
PA15
(JTDI)
JTDI/SPI3_NSS/
I2S3_WS/TIM2_CH1_ETR
/SPI1_NSS/EVENTOUT
78
PC10
SPI3_SCK/I2S3_CK/
UART4_TX/SDIO_D2/
DCMI_D8/USART3_TX/
EVENTOUT
79
PC11
UART4_RX/SPI3_MISO/
SDIO_D3/
DCMI_D4/USART3_RX/
I2S3ext_SD/EVENTOUT
80
PC12
UART5_TX/SDIO_CK/
DCMI_D9/SPI3_MOSI
/I2S3_SD/USART3_CK/
EVENTOUT
81
PD0
FSMC_D2/CAN1_RX/
EVENTOUT
82
PD1
FSMC_D3/CAN1_TX/
EVENTOUT
83
PD2
TIM3_ETR/UART5_RX/
SDIO_CMD/DCMI_D11/
EVENTOUT
84
PD3
FSMC_CLK/USART2_CTS
/EVENTOUT
85
PD4
FSMC_NOE/USART2_RTS
/EVENTOUT
86
PD5
FSMC_NWE/USART2_TX/
EVENTOUT
87
PD6
FSMC_NWAIT/
USART2_RX/EVENTOUT
88
PD7
USART2_CK/FSMC_NE1/
FSMC_NCE2/EVENTOUT
89
PB3
(JTDO/
TRACESWO)
JTDO/TRACESWO/
SPI3_SCK/I2S3_CK/
TIM2_CH2/SPI1_SCK
EVENTOUT
90
PB4
(NJTRST)
NJTRST/SPI3_MISO/
TIM3_CH1/SPI1_MISO/
I2S3ext_SD/EVENTOUT
91
PB5
I2C1_SMBA/CAN2_RX/
OTG_HS_ULPI_D7/
ETH_PPS_OUT/TIM3_CH
2/SPI1_MOSI/
SPI3_MOSI/DCMI_D10/
I2S3_SD/EVENTOUT
92
PB6
I2C1_SCL/TIM4_CH1/
CAN2_TX/
DCMI_D5/USART1_TX/
EVENTOUT
93
PB7
I2C1_SDA/FSMC_NL/
DCMI_VSYNC/
USART1_RX/TIM4_CH2/
EVENTOUT
94
BOOT0
95
PB8
TIM4_CH3/SDIO_D4/
TIM10_CH1/DCMI_D6/
ETH_MII_TXD3/
I2C1_SCL/CAN1_RX/
EVENTOUT
96
PB9
SPI2_NSS/I2S2_WS/
TIM4_CH4/TIM11_CH1/
SDIO_D5/DCMI_D7/
I2C1_SDA/CAN1_TX/
EVENTOUT
97
PE0
TIM4_ETR/FSMC_NBL0/
DCMI_D2/EVENTOUT
98
PE1
FSMC_NBL1/DCMI_D3/
EVENTOUT
99
VSS
100
VDD
一、输入、输出和高低电平说明:
在MODE栏里带括号的位置,前面的字母代表输入或者输出I=输入,O=输出,后面的数字代表高低电平1=高,0=低。
例:
接近开关J37(外门Y轴)(I/1),
代表接近开关以输入的方式,高电平有效。
二、串口TX1/RX1模式说明:
从机模式:
J50=2+3,J51=2+3
主机模式:
J50=2+1,J51=2+1
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- STM32F407VGT6 芯片 管脚 功能 定义
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