多功能数字钟课程设计VHDL代码书上程序改解析.docx
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多功能数字钟课程设计VHDL代码书上程序改解析.docx
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多功能数字钟课程设计VHDL代码书上程序改解析
libraryieee;
useieee.std_logic_1164.all;
entityclockis
port(
clk1hz:
instd_logic;--1hz脉冲--
clk100:
instd_logic;--100hz脉冲--
weekclk:
instd_logic;--星期调整脉冲--
start_stop:
instd_logic;--秒表启动/停止控制--
reset:
instd_logic;--秒表复位--
adclk:
instd_logic;--校时脉冲--
setselect:
instd_logic;--调整位选择脉冲--
mode:
instd_logic;--功能选择脉冲--
showdate:
instd_logic;--日期显示--
dis:
outstd_logic_vector(23downto0;--显示输出--glisten:
outstd_logic_vector(5downto0;--闪烁指示--weekout:
outstd_logic_vector(3downto0;--星期输出--qh:
outstd_logic--整点报时--
;
endclock;
architecturearchofclockis
componentadjust
port(
adclk:
instd_logic;
data_in:
outstd_logic_vector(7downto0
;
endcomponent;
componentcontrol
port(
setclk:
instd_logic;
setlap:
outstd_logic_vector(1downto0;
mode:
instd_logic;
module:
outstd_logic_vector(2downto0
;
endcomponent;
componentweekcounter
port(
clk:
instd_logic;
clk2:
instd_logic;
q:
outstd_logic_vector(3downto0
;
endcomponent;
componentstopwatch
port(
clk:
instd_logic;
reset:
instd_logic;
start_stop:
instd_logic;
centsec:
outstd_logic_vector(7downto0;
sec:
outstd_logic_vector(7downto0;
min:
outstd_logic_vector(7downto0
;
endcomponent;
componenth_m_s_count
port(
clk:
instd_logic;
set:
instd_logic;
setlap:
instd_logic_vector(1downto0;
d:
instd_logic_vector(7downto0;
sec:
outstd_logic_vector(7downto0;
min:
outstd_logic_vector(7downto0;
hour:
outstd_logic_vector(7downto0;
qh:
outstd_logic;
qc:
outstd_logic
;
endcomponent;
componenty_m_d_count
port(
clk:
instd_logic;
set:
instd_logic;
setlap:
instd_logic_vector(1downto0;
data_in:
instd_logic_vector(7downto0;
day:
outstd_logic_vector(7downto0;
month:
outstd_logic_vector(7downto0;
year:
outstd_logic_vector(7downto0
;
endcomponent;
componentdisplay
port(
module:
instd_logic_vector(2downto0;
showdate:
instd_logic;
clk:
instd_logic;
setlap:
instd_logic_vector(1downto0;
watch:
instd_logic_vector(23downto0;
time:
instd_logic_vector(23downto0;
date:
instd_logic_vector(23downto0;
dis:
outstd_logic_vector(23downto0;
glisten:
outstd_logic_vector(5downto0;
endcomponent;
signaldata_in,mcentsec,msec,mmin,ssec,smin,shour,sdate,smonth,syear:
std_logic_vector(7downto0;
signalsetlap:
std_logic_vector(1downto0;
signalmodule:
std_logic_vector(2downto0;
signalqc:
std_logic;
signalwatch,time,date:
std_logic_vector(23downto0;
begin
u1:
adjustportmap(adclk,data_in;
u2:
controlportmap(setselect,setlap,mode,module;
u3:
stopwatchportmap(clk100,reset,start_stop,mcentsec,msec,mmin;
u4:
h_m_s_countportmap(clk1hz,module(1,setlap,data_in,ssec,smin,shour,qh,qc;
u5:
y_m_d_countportmap(qc,module(2,setlap,data_in,sdate,smonth,syear;
u6:
displayportmap(module,showdate,clk1hz,setlap,watch,time,date,dis,glisten;
u7:
weekcounterportmap(qc,weekclk,weekout;
watch<=mmin&msec&mcentsec;
time<=shour&smin&ssec;
date<=syear&smonth&sdate;
endarch;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityadjustis
port(
adclk:
instd_logic;
data_in:
outstd_logic_vector(7downto0
;
endadjust;
architecturearchofadjustis
signaltemp2,temp1:
std_logic_vector(3downto0;
begin
process(adclk
begin
ifrising_edge(adclkthen
iftemp1="1001"then
temp2<=temp2+'1';
temp1<="0000";
else
temp1<=temp1+'1';
endif;
iftemp2="1001"andtemp1="1001"then
temp1<="0000";
temp2<="0000";
endif;
endif;
data_in<=temp2&temp1;
endprocess;
endarch;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycontrolis
port(
setclk:
instd_logic;--调整脉冲--
setlap:
outstd_logic_vector(1downto0;--调整位选择脉冲--mode:
instd_logic;--功能选择脉冲--
module:
outstd_logic_vector(2downto0--功能输出--
;
endcontrol;
architecturearchofcontrolis
signalssetlap:
std_logic_vector(1downto0;
signals:
std_logic_vector(3downto0;
begin
process(mode,setclk
begin
ifmode='1'then
ssetlap<="00";
elsifrising_edge(setclkthen
ifssetlap="10"then
ssetlap<="00";
else
ssetlap<=ssetlap+'1';
endif;
endif;
endprocess;
setlap<=ssetlap;
process(mode
begin
ifrising_edge(modethen
casesis
when"0001"=>s<="0010";
when"0010"=>s<="0100";
when"0100"=>s<="1000";
when"1000"=>s<="0001";
whenothers=>s<="0010";
endcase;
endif;
endprocess;
module<=s(3downto1;
endarch;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitycounter60is
port(
clk:
instd_logic;--计数脉冲--
clr:
instd_logic;--复位--
q:
outstd_logic_vector(7downto0;--计数值--qc:
outstd_logic--进位输出--
;
endcounter60;
architecturearchofcounter60is
signaltemp1,temp2:
std_logic_vector(3downto0;begin
process(clr,clk
begin
ifclr='1'then
temp1<="0000";
temp2<="0000";
elsifrising_edge(clkthen
iftemp1="1001"then
temp2<=temp2+'1';
temp1<="0000";
else
temp1<=temp1+'1';
endif;
iftemp2="0101"andtemp1="1001"then
temp1<="0000";
temp2<="0000";
qc<='1';
else
qc<='0';
endif;
endif;
q<=temp2&temp1;
endprocess;
endarch;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitycounter99is
port(
clk:
instd_logic;--100vhz计数脉冲--
en:
instd_logic;--计数使能--
clr:
instd_logic;--复位--
q:
outstd_logic_vector(7downto0;--计数值--
qc:
outstd_logic--进位--
;
endcounter99;
architecturearchofcounter99is
signaltemp1,temp2:
std_logic_vector(3downto0;begin
process(clr,clk
begin
ifclr='1'then
temp1<="0000";
temp2<="0000";
elsifrising_edge(clkthen
ifen='1'then
iftemp1="1001"then
temp2<=temp2+'1';
temp1<="0000";
else
temp1<=temp1+'1';
endif;
iftemp2="1001"andtemp1="1001"then
temp1<="0000";
temp2<="0000";
qc<='1';
else
qc<='0';
endif;
endif;
endif;
q<=temp2&temp1;
endprocess;
endarch;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitydaycounteris
port(
clk:
instd_logic;--计数脉冲--
set:
instd_logic;--调整信号--
day_in:
instd_logic_vector(7downto0;--调整输入--day_out:
outstd_logic_vector(7downto0;--天输出--qc:
outstd_logic;--进位--
day28:
instd_logic;--该位为1表示该月为28天--
day29:
instd_logic;--该位为1表示该月为29天--
day30:
instd_logic;--该位为1表示该月为30天--day31:
instd_logic--该位为1表示该月为31天--
;
enddaycounter;
architecturearchofdaycounteris
signaltemp1,temp2:
std_logic_vector(3downto0;signaldays:
std_logic_vector(7downto0;
begin
days<="00101000"whenday28='1'else
"00101001"whenday29='1'else
"00110000"whenday30='1'else"00110001"whenday31='1'else
"00000000";
process(clk,set,day_in,days
begin
ifset='1'then
temp2<=day_in(7downto4;
temp1<=day_in(3downto0;
elsifrising_edge(clkthen
iftemp1="1001"then
temp2<=temp2+'1';
temp1<="0000";
else
temp1<=temp1+'1';
endif;
iftemp2&temp1=daysthen
temp2<="0000";
temp1<="0001";
qc<='1';
else
qc<='0';
endif;
endif;
endprocess;
day_out<=temp2&temp1;
endarch;
libraryieee;
useieee.std_logic_1164.all;
entitydays_controlis
port(
month:
instd_logic_vector(7downto0;--月份--
year2:
instd_logic;--年份高位数字bcd码最低位--
year1:
instd_logic_vector(1downto0;--年份低位数字bcd码末两位--
day28:
outstd_logic;--该位为1表示该月为28天--
day29:
outstd_logic;--该位为1表示该月为29天--
day30:
outstd_logic;--该位为1表示该月为30天--
day31:
outstd_logic--该位为1表示该月为31天--
;
enddays_control;
architecturearchofdays_controlis
begin
process(month,year2,year1
begin
casemonthis
when"00000001"=>day28<='0';day29<='0';day30<='0';day31<='1';
when"00000010"=>if(year2='0'andyear1="00"or(year2='1'andyear1="10"thenday28<='0';day29<='1';day30<='0';day31<='0';
else
day28<='1';day29<='0';day30<='0';day31<='0';
endif;
when"00000011"=>day28<='0';day29<='0';day30<='0';day31<='1';
when"00000100"=>day28<='0';day29<='0';day30<='1';day31<='0';
when"00000101"=>day28<='0';day29<='0';day30<='0';day31<='1';
when"00000110"=>day28<='0';day29<='0';day30<='1';day31<='0';
when"00000111"=>day28<='0';day29<='0';day30<='0';day31<='1';
when"00001000"=>day28<='0';day29<='0';day30<='0';day31<='1';
when"00001001"=>day28<='0';day29<='0';day30<='1';day31<='0';
when"00010000"=>day28<='0';day29<='0';day30<='0';day31<='1';
when"00010001"=>day28<='0';day29<='0';day30<='1';day31<='0';
when"00010010"=>day28<='0';day29<='0';day30<='0';day31<='1';
whenothers=>day28<='0';day29<='0';day30<='0';day31<='1';
endcase;
endprocess;
endarch;
libraryieee;
useieee.std_logic_1164.all;
entitydisplayis
port(
module:
instd_logic_vector(2downto0;--功能选择--
showdate:
instd_logic;--显示日期--
clk:
instd_logic;--闪烁脉冲--
setlap:
instd_logic_vector(1downto0;--闪烁位选择--watch:
instd_logic_vector(23downto0;--秒表计数值输入--time:
instd_logic_vector(23downto0;--时分秒计数值输入--date:
instd_logic_vector(23downto0;--年月日计数值输入--dis:
outstd_logic_vector(23downto0;--显示输出--
glisten:
outstd_logic_vector(5downto0--闪烁输出--
;
enddisplay;
architecturearchofdisplayis
begin
process(module,showdate,watch,time,date
begin
ifshowdate='1'then
dis<=date;
else
casemoduleis
when"001"=>dis<=watch;
when"010"=>dis<=time;
when"100"=>dis<=date;
whenothers=>dis<=time;
endcase;
endif;
endprocess;
process(clk,module,setlap
begin
ifmodule="010"ormodule="100"then
casesetlapis
when"00"=>glisten(1downto0<=clk&clk;
glisten(5downto2<="0000";
when"01"=>glisten(3downto2<=clk&clk;
glisten(5downto4<="00";
glisten(1downto0<="00";
when"10"=>glisten(5downto4<=clk&clk;
glisten(3downto0<="0000";
whenothers=>glisten<="000000";
endcase;
elseglisten<="000000";
endif;
endprocess;
endarch;
libraryieee;
useieee.std_logic_1164.all;
entitydmuxis
port(
set:
instd_logic;--调整信号--
setlap:
instd_logic_vector(1downto0;--调整位选择--d:
instd_logic_vector(7downto0;--调整输入--
set1:
outstd_logic;
set2:
outstd_logic;
set3:
out
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