21按键简易电子琴可自动播放乐曲知识讲解.docx
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21按键简易电子琴可自动播放乐曲知识讲解.docx
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21按键简易电子琴可自动播放乐曲知识讲解
21按键简易电子琴可自动播放乐曲
课程设计报告
课程名称:
FPGA课程设计(EDA技术及应用)
题目:
基于FPGA的简易电子琴设计
学院:
物理与电子工程学院
专业:
电子信息工程
班级:
学号:
学生姓名:
指导教师:
起讫日期:
基于FPGA的简易电子琴设计
物理与电子工程学院电子信息工程
1设计目的任务及要求
1简易电子琴
1)设计一个能发出7个音阶的系统并能多种模式播放歌曲(歌曲可自定,至少3首)
2)利用一基准脉冲产生1,2,3,。
。
。
共7个音阶信号,进行弹奏;
3)用指示灯显示节拍;
4)*能对弹奏乐曲存储并回放。
1.1设计目的
1、熟悉VHDL语言
2、学习电子琴的设计,调试,仿真以及对仿真波形的调试
1.2设计要求(简易电子琴的功能)
1、设计一个能发出7个音阶的系统并能多种模式播放歌曲(歌曲可自定,至少首)
2、利用一基准脉冲产生1,2,3,。
。
。
共7个音阶信号,进行弹奏;
3、用指示灯显示节拍;
4、*能对弹奏乐曲存储并回放。
2、设计内容
自动播放Notetabs
二选一选择器mux21c
分频预置数ToneTabs
一)、设计思路
按键输入
按键输入判断ceshi
按键去抖动
FEN
按键输出
SWI
分频器SPEAKER
发出音乐
spkout
二)、设计实现
本设计实现了能发出底、中、高三个节拍的7个音阶的系统,整个系统共有3首歌曲,这三首歌曲具有顺序播放和随机切换歌曲的播放功能。
能随意弹奏每首歌曲,同时具有数码管显示每个音阶所对应的阿拉伯数字,不同的节拍我们也有相应的指示灯作为区分,在低音时无指示灯亮,中音时有一个亮,高音时有两个指示灯亮。
1)按键输入的判断:
a.代码
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYceshiIS
PORT(s:
INSTD_LOGIC;
Y:
outstd_logic);
ENDENTITYceshi;
ARCHITECTUREFUNOFceshiIS
begin
PROCESS(s)
BEGIN
IFs='1'THENY<='1';
ELSEy<='0';
endif;
endprocess;
ENDARCHITECTUREFUN;
b.波形仿真图
2)按键去抖动
a.代码
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYFENIS
PORT(CLK,KIN:
INSTD_LOGIC;
KOUT:
OUTSTD_LOGIC);
END;
ARCHITECTUREBHVOFFENIS
SIGNALKL,KH:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PROCESS(CLK,KIN,KL,KH)BEGIN
IFCLK'EVENTANDCLK='1'THEN
IF(KIN='0')THENKL<=KL+1;
ELSEKL<="0000";ENDIF;
IF(KIN='1')THENKH<=KH+1;
ELSEKH<="0000";ENDIF;
IF(KH>"1100")THENKOUT<='1';
ELSIF(KL>"0111")THENKOUT<='0';
ENDIF;
ENDIF;
ENDPROCESS;
END;
b.波形仿真图
3)产生节拍控制和音阶选择信号
a.代码
3)音乐自动播放
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYNOTETABSIS
PORT(CLK:
INSTD_LOGIC;
S:
INSTD_LOGIC_VECTOR(1DOWNTO0);
TONEINDEX:
OUTSTD_LOGIC_VECTOR(4DOWNTO0));
ENDENTITYNOTETABS;
ARCHITECTUREFUNOFNOTETABSIS
COMPONENTMUSIC
PORT
(
address:
INSTD_LOGIC_VECTOR(8DOWNTO0);
clock:
INSTD_LOGIC;
q:
OUTSTD_LOGIC_VECTOR(4DOWNTO0)
);
ENDCOMPONENT;
SIGNALCOUNTER:
STD_LOGIC_VECTOR(8DOWNTO0);
BEGIN
PROCESS(CLK,COUNTER)
BEGIN
IF(COUNTER=432)THENCOUNTER<="000000000";
ELSIF(CLK'EVENTANDCLK='1')THENCOUNTER<=COUNTER+1;
ENDIF;
IF(S="11"ANDCOUNTER>144)THENCOUNTER<="000000000";
ELSIF(S="10"AND(COUNTER<144ORCOUNTER>288))THENCOUNTER<="010010000";
ELSIF(S="01"AND(COUNTER<288ORCOUNTER>432))THENCOUNTER<="100100000";
ELSE
ENDIF;
ENDPROCESS;
U1:
MUSICPORTMAP(address=>COUNTER,q=>TONEINDEX,clock=>CLK);
ENDARCHITECTUREFUN;
b.波形仿真图
4)二选一选择器
a.代码
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux21cIS
PORT(k_code,toneindex:
INSTD_LOGIC_VECTOR(4DOWNTO0);
key:
INSTD_LOGIC;
index:
OUTSTD_LOGIC_VECTOR(4DOWNTO0));
END;
ARCHITECTUREfiveOFmux21cIS
BEGIN
PROCESS(k_code,toneindex,key)
BEGIN
IFkey='1'THENindex<=k_code;
ELSEindex<=toneindex;
ENDIF;
ENDPROCESS;
ENDfive;
b.波形仿真图
5)按键的输出
a.代码
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYSWIIS
PORT(A,B,C,D,E,F,G,H,I,K,L,M,N,O,P,Q,R,S,T,U:
INSTD_LOGIC;
Y:
OUTSTD_LOGIC_VECTOR(4DOWNTO0));
ENDENTITYSWI;
ARCHITECTUREFUNOFSWIIS
SIGNALJ:
STD_LOGIC_VECTOR(19DOWNTO0);
BEGIN
J<=A&B&C&D&E&F&G&H&I&K&L&M&N&O&P&Q&R&S&T&U;
P1:
PROCESS(J)
BEGIN
CASE(J)IS
when"11111111111111111111"=>Y<="00000";
WHEN"11111111111111111110"=>Y<="00001";
WHEN"11111111111111111101"=>Y<="00010";
WHEN"11111111111111111011"=>Y<="00011";
WHEN"11111111111111110111"=>Y<="00100";
WHEN"11111111111111101111"=>Y<="00101";
WHEN"11111111111111011111"=>Y<="00110";
WHEN"11111111111110111111"=>Y<="00111";
WHEN"11111111111101111111"=>Y<="01000";
WHEN"11111111111011111111"=>Y<="01001";
WHEN"11111111110111111111"=>Y<="01010";
WHEN"11111111101111111111"=>Y<="01011";
WHEN"11111111011111111111"=>Y<="01100";
WHEN"11111110111111111111"=>Y<="01101";
WHEN"11111101111111111111"=>Y<="01110";
WHEN"11111011111111111111"=>Y<="01111";
WHEN"11110111111111111111"=>Y<="10000";
WHEN"11101111111111111111"=>Y<="10001";
WHEN"11011111111111111111"=>Y<="10010";
WHEN"10111111111111111111"=>Y<="10011";
WHEN"01111111111111111111"=>Y<="10100";
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESSP1;
ENDARCHITECTUREFUN;
b.波形仿真图
6)分频预置数的产生
a.代码
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYToneTabaIS
PORT(Index:
INSTD_LOGIC_VECTOR(4DOWNTO0);
CODE:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
HIGH1,HIGH2:
OUTSTD_LOGIC;
Tone:
OUTSTD_LOGIC_VECTOR(10DOWNTO0));
END;
ARCHITECTUREoneOFToneTabaIS
BEGIN
Search:
PROCESS(Index)
BEGIN
CASEIndexIS
WHEN"00000"=>Tone<="11111111111";CODE<="0000";HIGH1<='0';HIGH2<='0';
WHEN"00001"=>Tone<="01100000101";CODE<="0001";HIGH1<='0';HIGH2<='0';--773;
WHEN"00010"=>Tone<="01110010000";CODE<="0010";HIGH1<='0';HIGH2<='0';--912;
WHEN"00011"=>Tone<="10000001100";CODE<="0011";HIGH1<='0';HIGH2<='0';--1036;
when"00100"=>Tone<="10001000100";CODE<="0100";HIGH1<='0';HIGH2<='0';
WHEN"00101"=>Tone<="10010101101";CODE<="0101";HIGH1<='0';HIGH2<='0';--1197;
WHEN"00110"=>Tone<="10100001010";CODE<="0110";HIGH1<='0';HIGH2<='0';--1290;
WHEN"00111"=>Tone<="10101011100";CODE<="0111";HIGH1<='0';HIGH2<='0';--1372;
WHEN"01000"=>Tone<="10110000010";CODE<="0001";HIGH1<='1';HIGH2<='0';--1410;
WHEN"01001"=>Tone<="10111001000";CODE<="0010";HIGH1<='1';HIGH2<='0';--1480;
WHEN"01010"=>Tone<="11000000110";CODE<="0011";HIGH1<='1';HIGH2<='0';--1542;
when"01011"=>Tone<="11000100010";CODE<="0100";HIGH1<='1';HIGH2<='0';
WHEN"01100"=>Tone<="11001010110";CODE<="0101";HIGH1<='1';HIGH2<='0';--1622;
WHEN"01101"=>Tone<="11010000100";CODE<="0110";HIGH1<='1';HIGH2<='0';--1668;
when"01110"=>Tone<="11010011010";CODE<="0111";HIGH1<='1';HIGH2<='0';
WHEN"01111"=>Tone<="11011000000";CODE<="0001";HIGH1<='1';HIGH2<='1';--1728;
WHEN"10000"=>Tone<="11011100100";CODE<="0010";HIGH1<='1';HIGH2<='1';
WHEN"10001"=>Tone<="11100000011";CODE<="0011";HIGH1<='1';HIGH2<='1';
WHEN"10010"=>Tone<="11100010001";CODE<="0100";HIGH1<='1';HIGH2<='1';
WHEN"10011"=>Tone<="11100001011";CODE<="0101";HIGH1<='1';HIGH2<='1';
WHEN"10100"=>Tone<="11101000010";CODE<="0110";HIGH1<='1';HIGH2<='1';
WHEN"10101"=>Tone<="11101001100";CODE<="0111";HIGH1<='1';HIGH2<='1';
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
END;
b.波形仿真图
7)分频器
a.代码
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYSPEAKERIS
PORT(CLK:
INSTD_LOGIC;
TONE:
INSTD_LOGIC_VECTOR(10DOWNTO0);
SPKS:
OUTSTD_LOGIC);
ENDENTITYSPEAKER;
ARCHITECTUREFUNOFSPEAKERIS
SIGNALPRECLK,FULLSPKS:
STD_LOGIC;
BEGIN
PROCESS(CLK)
VARIABLECOUNT4:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PRECLK<='0';
IFCOUNT4>11THENPRECLK<='1';COUNT4:
="0000";
ELSIFCLK'EVENTANDCLK='1'THENCOUNT4:
=COUNT4+1;
ENDIF;
ENDPROCESS;
PROCESS(PRECLK,TONE)
VARIABLECOUNT11:
STD_LOGIC_VECTOR(10DOWNTO0);
BEGIN
IFPRECLK'EVENTANDPRECLK='1'THEN
IFCOUNT11=16#7FF#THENCOUNT11:
=TONE;FULLSPKS<='1';
ELSECOUNT11:
=COUNT11+1;FULLSPKS<='0';
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS(FULLSPKS)
VARIABLECOUNT2:
STD_LOGIC;
BEGIN
IFFULLSPKS'EVENTANDFULLSPKS='1'THENCOUNT2:
=NOTCOUNT2;
IFCOUNT2='1'THENSPKS<='1';
ELSESPKS<='0';
ENDIF;
ENDIF;
ENDPROCESS;
ENDARCHITECTUREFUN;
b.波形仿真图
3、系统仿真与调试
A、原理图:
B、波形仿真
C、PCB图:
D、调试图:
5、主要参考文献
[1]潘松黄继业EDA技术实用数据VHDL版(第五版)科学出版社2013
[2]曹昕燕,周凤臣.EDA技术实验与课程设计.清华大学出版社,2006.
[3]阎石,数学电子技术基础.高等教育出版社,2003.
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