常用EDA程序集.docx
- 文档编号:2376627
- 上传时间:2022-10-29
- 格式:DOCX
- 页数:14
- 大小:16.73KB
常用EDA程序集.docx
《常用EDA程序集.docx》由会员分享,可在线阅读,更多相关《常用EDA程序集.docx(14页珍藏版)》请在冰豆网上搜索。
常用EDA程序集
一位加法器
libraryieee;
useieee.std_logic_1164.all;
entityadder1is
port(a,b:
instd_logic;
cin:
instd_logic;
so,co:
outstd_logic);
endadder1;
architectureoneofadder1is
begin
so<=(axorb)xorcin;
co<=(aandb)or(aandcin)or(bandcin);
endone;
程序包
libraryieee;
useieee.std_logic_1164.all;
packagemy_pkgis
componentadder1
port(a,b:
instd_logic;
cin:
instd_logic;
so,co:
outstd_logic);
endcomponent;
endmy_pkg;
4位加法器
libraryieee;
useieee.std_logic_1164.all;
usework.my_pkg.all;
entityadder4is
port(a,b:
instd_logic_vector(3downto0);
cin:
instd_logic;
sum:
outstd_logic_vector(3downto0);
cout:
outstd_logic);
endadder4;
architectureadder4behvofadder4is
signald:
std_logic_vector(1to3);
begin
u1:
adder1portmap(a(0),b(0),cin,sum(0),d
(1));
u2:
adder1portmap(a
(1),b
(1),d
(1),sum
(1),d
(2));
u3:
adder1portmap(a
(2),b
(2),d
(2),sum
(2),d(3));
u4:
adder1portmap(a(3),b(3),d(3),sum(3),cout);
endadder4behv;
4位移位寄存器
libraryieee;
useieee.std_logic_1164.all;
entitydff1is
port(d,clk:
instd_logic;
q:
outstd_logic);
enddff1;
architectureoneofdff1is
signalu:
std_logic:
='0';
begin
process(d,clk,u)
begin
if(clk'eventandclk='1')then
u<=d;
endif;
q<=u;
endprocess;
endone;
libraryieee;
useieee.std_logic_1164.all;
entityshifteris
port(d0,clk:
instd_logic;
q0:
outstd_logic);
endshifter;
architectureonesofshifteris
componentdff1
port(d,clk:
instd_logic;
q:
outstd_logic);
endcomponent;
signala:
std_logic_vector(1to3);
begin
u1:
dff1portmap(d0,clk,a
(1));
u2:
dff1portmap(a
(1),clk,a
(2));
u3:
dff1portmap(a
(2),clk,a(3));
u4:
dff1portmap(a(3),clk,q0);
endones;
4位二进制计数器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYcnt4eIS
port(clr,clk,ena:
INSTD_LOGIC;
cout:
OUTSTD_LOGIC;
q:
BUFFERINTEGERRANGE0TO15);
ENDcnt4e;
ARCHITECTUREONEOFcnt4eIS
BEGIN
PROCESS(clr,clk,ena)
BEGIN
IFclr='0'then
q<=0;cout<='0';
elsifclk'EVENTANDclk='1'THEN
ifena='1'then
ifq=15thenq<=0;
cout<='0';
elsifq=14Thenq<=q+1;
cout<='1';
elseq<=q+1;
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
ENDONE;
4选1数据选择器
libraryieee;
useieee.std_logic_1164.all;
entitymux4_1is
port(a,b,c,d:
instd_logic;
s0,s1:
instd_logic;
y:
outstd_logic);
endmux4_1;
architecturegoodofmux4_1is
signals:
std_logic_vector(1downto0);
begin
s<=s1&s0;
process(a,b,c,d,s)
begin
casesis
when"00"=>y<=a;
when"01"=>y<=b;
when"10"=>y<=c;
when"11"=>y<=d;
whenothers=>y<='X';
endcase;
endprocess;
endgood;
程序包
libraryieee;
useieee.std_logic_1164.all;
packagemy_pkgis
componentmux4_1
port(a,b,c,d:
instd_logic;
s0,s1:
instd_logic;
y:
outstd_logic);
endcomponent;
endmy_pkg;
双4选1
libraryieee;
useieee.std_logic_1164.all;
usework.my_pkg.all;
entityddmux4_1is
port(a,b,c,d:
instd_logic_vector(3downto0);
s0,s1:
instd_logic;
y:
outstd_logic_vector(3downto0));
endddmux4_1;
architectureoneofddmux4_1is
signalu:
std_logic_vector(3downto0);
beginlab1:
fornin0to3generate
ux:
mux4_1portmap(a(n),b(n),c(n),d(n),s0,s1,u(n));
endgenerate;
y<=u;
endone;
38译码器
libraryieee;
useieee.std_logic_1164.all;
entitydecode38is
port(y:
instd_logic_vector(2downto0);
a:
outstd_logic_vector(7downto0));
enddecode38;
architectureoneofdecode38is
begin
process(y)
begin
if(y<="000")thena<="11111110";
elsif(y<="001")thena<="11111101";
elsif(y<="010")thena<="11111011";
elsif(y<="011")thena<="11110111";
elsif(y<="100")thena<="11101111";
elsif(y<="101")thena<="11011111";
elsif(y<="110")thena<="10111111";
elsif(y<="111")thena<="01111111";
elsea<="11111111";
endif;
endprocess;
endone;
D触发器
libraryieee;
useieee.std_logic_1164.all;
entitydtriggeris
port(clk,d,clr:
instd_logic;
q:
outstd_logic);
enddtrigger;
architectureoneofdtriggeris
begin
process(clk,d,clr)
begin
if(clr='0')thenq<='0';
elsif(clk'eventandclk='1')thenq<=d;
endif;
endprocess;
endone;
1位减法器:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.all;
entitysubber1is
port(a,b,cin:
instd_logic;
s:
outstd_logic;
cout:
outstd_logic);
endsubber1;
architectureoneofsubber1is
begin
s<=(axorb)xorcin;
cout<=((nota)nandb)nand(not(axorb)nandcin);
endone;
4位减法器:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEWORK.my_pkg.all;
entitysubber4is
port(a,b:
instd_logic_vector(3downto0);
cin:
instd_logic;
s:
outstd_logic_vector(3downto0);
cout:
outstd_logic);
endsubber4;
architectureoneofsubber4is
signalcout0,cout1,cout2:
std_logic;
begin
u1:
subber1portmap(a(0),b(0),cin,s(0),cout0);
u2:
subber1portmap(a
(1),b
(1),cout0,s
(1),cout1);
u3:
subber1portmap(a
(2),b
(2),cout1,s
(2),cout2);
u4:
subber1portmap(a(3),b(3),cout2,s(3),cout);
endone;
程序包:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.A
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- 常用 EDA 程序
![提示](https://static.bdocx.com/images/bang_tan.gif)