EDA数字秒表课程设计.docx
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- 上传时间:2023-05-16
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EDA数字秒表课程设计.docx
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EDA数字秒表课程设计
程序:
(1)时基分频模块的VHDL源程序(CB10.VHD)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCB10IS
PORT(CLK:
INSTD_LOGIC;——输入时钟信号
CO:
OUTSTD_LOGIC);——分频输出信号
ENDCB10;——实体描述
ARCHITECTUREARTOFCB10IS——结构体描述
SIGNALCOUNT:
STD_LOGIC_VECTOR(3DOWNTO0);
——硬件系统的基本数据对象
BEGIN
PROCESS(CLK)——进程敏感信号
BEGIN
IFRISING_EDGE(CLK)THEN
IFCOUNT="1001"THEN
COUNT<="0000";
CO<='1';
ELSE
COUNT<=COUNT+1;
CO<='0';
ENDIF;
ENDIF;
ENDPROCESS;
ENDART;
(2)控制模块的VHDL源程序(CTRL.VHD)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCTRLIS
PORT(CLR,CLK,SP:
INSTD_LOGIC;
EN:
OUTSTD_LOGIC);——CLR:
清零信号
CLK:
脉冲输入端
SP:
计数输入端
EN:
输出端
END;
ARCHITECTUREBEHAVEOFCTRLIS
CONSTANTS0:
STD_LOGIC_VECTOR(1DOWNTO0):
="00";
CONSTANTS1:
STD_LOGIC_VECTOR(1DOWNTO0):
="01";
CONSTANTS2:
STD_LOGIC_VECTOR(1DOWNTO0):
="10";
CONSTANTS3:
STD_LOGIC_VECTOR(1DOWNTO0):
="11";
TYPESTATESIS(S0,S1,S2,S3);——表达四个状态的位矢量
SIGNALCURRENT_STATE,NEXT_STATE:
STATES;
BEGIN
COM:
PROCESS(SP,CURRENT_STATE)——决定转换状态的进程
BEGIN
CASECURRENT_STATEIS
WHENS0=>EN<='0';——选中状态为S0、EN='0'
IFSP='1'THEN
NEXT_STATE<=S1;
ELSE
NEXT_STATE<=S0;
ENDIF;
WHENS1=>EN<='1';——选中状态为S1、EN='1'
IFSP='1'THEN
NEXT_STATE<=S1;
ELSE
NEXT_STATE<=S2;
ENDIF;
WHENS2=>EN<='1';——选中状态为S2、EN='1'
IFSP='1'THEN
NEXT_STATE<=S3;
ELSE
NEXT_STATE<=S2;
ENDIF;
WHENS3=>EN<='0';——选中状态为S3、EN='0'
IFSP='1'THEN
NEXT_STATE<=S3;
ELSE
NEXT_STATE<=S0;
ENDIF;
ENDCASE;
ENDPROCESS;
SYNCH:
PROCESS(CLK)——时序进程
BEGIN
IFCLR='1'THEN
CURRENT_STATE<=S0;
ELSIFCLK'EVENTANDCLK='1'THEN
CURRENT_STATE<=NEXT_STATE;
ENDIF;
ENDPROCESS;
ENDBEHAVE;
(3)计时模块的VHDL源程序
①十进制计数器的VHDL源程序——cdu10.vhd
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYcdu10IS
PORT(CLK:
INSTD_LOGIC;——时钟信号
CLR:
INSTD_LOGIC;——清零信号
EN:
INSTD_LOGIC;——计数使能信号
CN:
OUTSTD_LOGIC;——计数输出信号
COUNT10:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));——计数值
ENDcdu10;
ARCHITECTUREARTOFcdu10IS
SIGNALSCOUNT10:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
COUNT10<=SCOUNT10;
PROCESS(CLK,CLR,EN)
BEGIN
IF(CLR='1')THEN
SCOUNT10<="0000";CN<='0';
ELSIFRISING_EDGE(CLK)THEN——脉冲为上跳沿触发
IF(EN='1')THEN
IFSCOUNT10="1001"THEN
CN<='1';
SCOUNT10<="0000";
ELSE
CN<='0';
SCOUNT10<=SCOUNT10+'1';
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
ENDART;
②六进制计数器的VHDL源程序——cdu6.vhd
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYcdu6IS
PORT(CLK:
INSTD_LOGIC;
CLR:
INSTD_LOGIC;
EN:
INSTD_LOGIC;
CN:
OUTSTD_LOGIC;——计数输出信号
COUNT6:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));——计数值
ENDcdu6;
ARCHITECTUREARTOFcdu6IS
SIGNALSCOUNT6:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
COUNT6<=SCOUNT6;
PROCESS(CLK,CLR,EN)
BEGIN
IF(CLR='1')THEN
SCOUNT6<="0000";CN<='0';
ELSIFRISING_EDGE(CLK)THEN
IF(EN='1')THEN
IFSCOUNT6="0101"THEN
CN<='1';
SCOUNT6<="0000";
ELSE
CN<='0';
SCOUNT6<=SCOUNT6+'1';
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
ENDART;
③计时器的VHDL源程序——count.vhd
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYcountIS
PORT(CLK:
INSTD_LOGIC;
CLR:
INSTD_LOGIC;
EN:
INSTD_LOGIC;
S_1MS:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);——毫秒计数值
S_10MS:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);——十毫秒计数值
S_100MS:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);——百毫秒计数值
S_1S:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);——秒计数值
S_10S:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);——十秒计数值
M_1MIN:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);——分计数值
M_10MIN:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);——十分计数值
HOUR:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));——小时计数值
ENDcount;
ARCHITECTUREARTOFcountIS
COMPONENTcdu10——元件例化
PORT(CLK:
INSTD_LOGIC;
CLR:
INSTD_LOGIC;
EN:
INSTD_LOGIC;
CN:
OUTSTD_LOGIC;
COUNT10:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDCOMPONENTcdu10;
COMPONENTcdu6——元件例化
PORT(CLK:
INSTD_LOGIC;
CLR:
INSTD_LOGIC;
EN:
INSTD_LOGIC;
CN:
OUTSTD_LOGIC;
COUNT6:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDCOMPONENTcdu6;
SIGNALA,B,C,D,E,F,G,H:
STD_LOGIC;
BEGIN
U1:
cdu10PORTMAP(CLK,CLR,EN,A,S_1MS);
U2:
cdu10PORTMAP(A,CLR,EN,B,S_10MS);
U3:
cdu10PORTMAP(B,CLR,EN,C,S_100MS);
U4:
cdu10PORTMAP(C,CLR,EN,D,S_1S);
U5:
cdu6PORTMAP(D,CLR,EN,E,S_10S);
U6:
cdu10PORTMAP(E,CLR,EN,F,M_1MIN);
U7:
cdu6PORTMAP(F,CLR,EN,G,M_10MIN);
U8:
cdu10PORTMAP(G,CLR,EN,H,HOUR);
ENDART;
(4)显示模块的VHDL源程序
数据选择器的VHDL源程序(MULX.VHD)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYMULXIS
PORT(CLK,CLR,EN:
INSTD_LOGIC;
S_1MS:
INSTD_LOGIC_VECTOR(3DOWNTO0);——毫秒计数器
S_10MS:
INSTD_LOGIC_VECTOR(3DOWNTO0);——十毫秒计数器
S_100MS:
INSTD_LOGIC_VECTOR(3DOWNTO0);——百毫秒计数器
S_1S:
INSTD_LOGIC_VECTOR(3DOWNTO0);——秒计数器
S_10S:
INSTD_LOGIC_VECTOR(3DOWNTO0);——十秒计数器
M_1MIN:
INSTD_LOGIC_VECTOR(3DOWNTO0);——分计数器
M_10MIN:
INSTD_LOGIC_VECTOR(3DOWNTO0);——十分计数器
HOUR:
INSTD_LOGIC_VECTOR(3DOWNTO0);——小时计数器
OUTBCD:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);——BCD码输出
SEG:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));——七段译码输出
ENDMULX;
ARCHITECTUREARTOFMULXIS
SIGNALCOUNT:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PROCESS(CLK)
BEGIN
IFCLR='1'THEN
COUNT<="1111";
ELSIFRISING_EDGE(CLK)THEN
IFEN='1'THEN
IFCOUNT="1001"THEN
COUNT<="0000";
ELSE
COUNT<=COUNT+1;
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS(CLK)
BEGIN
IFCLK'EVENTANDCLK='1'THEN——时钟上升沿触发输出各位数据
CASECOUNTIS
WHEN"0000"=>OUTBCD<=S_1MS;SEG<="11111110";
WHEN"0001"=>OUTBCD<=S_10MS;SEG<="11111101";
WHEN"0010"=>OUTBCD<=S_100MS;SEG<="11111011";
WHEN"0011"=>OUTBCD<=S_1S;SEG<="11110111";
WHEN"0100"=>OUTBCD<=S_10S;SEG<="11101111";
WHEN"0101"=>OUTBCD<=M_1MIN;SEG<="11011111";
WHEN"0110"=>OUTBCD<=M_10MIN;SEG<="10111111";
WHEN"0111"=>OUTBCD<=HOUR;SEG<="01111111";
WHEN"1000"=>OUTBCD<=S_1MS;SEG<="11111110";
WHEN"1001"=>OUTBCD<=S_10MS;SEG<="11111101";
WHENOTHERS=>OUTBCD<="0000";SEG<="00000000";
ENDCASE;
ENDIF;
ENDPROCESS;
ENDART;
BCD七段译码驱动器的VHDL源程序(BCD.VHD)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYBCD7IS
PORT(BCD:
INSTD_LOGIC_VECTOR(3DOWNTO0);
——输入为4位二进制数,范围从0到9
LED:
OUTSTD_LOGIC_VECTOR(6DOWNTO0));
——7段译码输出
ENDBCD7;
ARCHITECTUREARTOFBCD7IS
BEGIN
LED<="1111110"WHENBCD="0000"ELSE——0的7段译码(以下类推)
"0110000"WHENBCD="0001"ELSE
"1101101"WHENBCD="0010"ELSE
"1111001"WHENBCD="0011"ELSE
"0110011"WHENBCD="0100"ELSE
"1011011"WHENBCD="0101"ELSE
"1011111"WHENBCD="0110"ELSE
"1110000"WHENBCD="1000"ELSE
"1111011"WHENBCD="1001"ELSE
"0000000";——其他情况的输出
ENDART;
(5)顶层设计的的VHDL源程序(mb.vhd)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmbIS
PORT(SP:
INSTD_LOGIC;
CLR:
INSTD_LOGIC;
CLK:
INSTD_LOGIC;
CO:
OUTSTD_LOGIC;
EN:
OUTSTD_LOGIC;
LED:
OUTSTD_LOGIC_VECTOR(6DOWNTO0);
OUTBCD:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
SEG:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDmb;
ARCHITECTUREARTOFmbIS
COMPONENTCTRL
PORT(SP:
INSTD_LOGIC;
CLR:
INSTD_LOGIC;
CLK:
INSTD_LOGIC;
EN:
OUTSTD_LOGIC);
ENDCOMPONENT;
COMPONENTCB10
PORT(CLK:
INSTD_LOGIC;
CO:
OUTSTD_LOGIC);
ENDCOMPONENT;
COMPONENTcount
PORT(CLK:
INSTD_LOGIC;
CLR:
INSTD_LOGIC;
EN:
INSTD_LOGIC;
S_1MS:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
S_10MS:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
S_100MS:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
S_1S:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
S_10S:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
M_1MIN:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
M_10MIN:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
HOUR:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDCOMPONENT;
COMPONENTBCD7
PORT(BCD:
INSTD_LOGIC_VECTOR(3DOWNTO0);
LED:
OUTSTD_LOGIC_VECTOR(6DOWNTO0));
ENDCOMPONENT;
COMPONENTMULX
PORT(CLK:
INSTD_LOGIC;
CLR:
INSTD_LOGIC;
EN:
INSTD_LOGIC;
S_1MS:
INSTD_LOGIC_VECTOR(3DOWNTO0);
S_10MS:
INSTD_LOGIC_VECTOR(3DOWNTO0);
S_100MS:
INSTD_LOGIC_VECTOR(3DOWNTO0);
S_1S:
INSTD_LOGIC_VECTOR(3DOWNTO0);
S_10S:
INSTD_LOGIC_VECTOR(3DOWNTO0);
M_1MIN:
INSTD_LOGIC_VECTOR(3DOWNTO0);
M_10MIN:
INSTD_LOGIC_VECTOR(3DOWNTO0);
HOUR:
INSTD_LOGIC_VECTOR(3DOWNTO0);
OUTBCD:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
SEG:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDCOMPONENT;
SIGNALC,E:
STD_LOGIC;
SIGNALMS1_S,MS10_S,MS100_S:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALS1S_S,S10_S:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALMIN1_S,MIN10_S:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALH:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALBCD_S:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
U0:
CTRLPORTMAP(CLR,CLK,SP,E);
U1:
CB10PORTMAP(CLK,C);
U2:
countPORTMAP(C,CLR,E,MS1_S,MS10_S,MS100_S,S1S_S,S10_S,MIN1_S,MIN10_S,H);
U3:
MULXPORTMAP(CLR,CLK,E,MS1_S,MS10_S,MS100_S,S1S_S,S10_S,MIN1_S,MIN10_S,H,BCD_S,SEG);
U4:
BCD7PORTMAP(BCD_S,LED);
CO<=C;
EN<=E;
OUTBCD<=BCD_S;
ENDART;
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- 关 键 词:
- EDA 数字 秒表 课程设计