ZBTsram控制器VHDL.docx

ZBTsram控制器VHDL.docx

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ZBTsram控制器VHDL

----------------------------------------------------------------------------------

--Company:

VISENGIS.L.（）-URJCFRAVGroup（www.frav.es）

--Engineer:

VictorLopezLorenzo（victor.lopez（at）visengi（dot）com）

--

--CreateDate:

12:

39:

5006-Oct-2008

--ProjectName:

ZBT（zero-busturnaround）SRAMWISHBONEController{SyncBurstSRAMandZBTSRAM}

--TargetDevices:

XilinxML506board

--Toolversions:

XilinxISE9.2i

--Description:

ThisisaZBTSRAMcontrollerwhichisWishbonerevB.3compatible（classic+burstr/woperations）.

--

--Dependencies:

Itmayberunonanyboard/FPGAwithaZBTSRAMpincompatible（oratleastinthecontrolsignals）

--withtheoneontheML506board（ISSIIS61NLP256kx36ZBTSRAM）

--

--

--LICENSETERMS:

（CCPL）CreativeCommonsAttribution-Noncommercial-ShareAlike3.0Unported.

--http:

//creativecommons.org/licenses/by-nc-sa/3.0/

--

--ThatisyoumayuseitonlyinNON-COMMERCIALprojects.

--Youarerequiredtoincludeinthecopyrights/aboutsection

--thatyoursystemcontainsa"ZBTSRAMController（C）VictorLopezLorenzounderCCPLlicense"

--Thisholdsalsointhecasewhereyoumodifythecore,astheresultingcore

--wouldbeaderivedwork.

--Also,wewouldliketoknowifyouusethiscoreinaprojectofyours,justanemailwilldo.

--

--PleasetakegoodnoteofthedisclaimersectionoftheCCPLlicense,aswedon't

--takeanyresponsabilityforanythingthatthiscoredoes.

----------------------------------------------------------------------------------

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_ARITH.ALL;

useIEEE.STD_LOGIC_UNSIGNED.ALL;

--WB:

MASTERMUSTNOTinsertwaitstates!

--WB:

maximumburstlengthis4（butburstsmayfollowwithoutwaitstatesinbetween）

entityzbt_topis

Port（clk:

inSTD_LOGIC;

reset:

inSTD_LOGIC;

SRAM_CLK:

outSTD_LOGIC;--SynchronousClock（upto200MHz）

--Aburstmodepin（MODE）definestheorderoftheburstsequence.WhentiedHIGH,theinterleavedburstsequenceisselected.

--WhentiedLOW,thelinearburstsequenceisselected.

SRAM_MODE:

outSTD_LOGIC;--BurstSequenceSelection（pulleddownonPCB）

SRAM_CS_B:

outSTD_LOGIC;--SynchronousChipEnable（CE\,pulleduponPCB）

--Forwritecyclesfollowingreadcycles,theoutputbuffersmustbedisabledwithOE\,otherwisedatabuscontentionwilloccur

SRAM_OE_B:

outSTD_LOGIC;--OutputEnable（OE\,pulleduponPCB）

--Writecyclesareinternallyself-timedandareinitiatedbytherisingedgeoftheclockinputsandwhenWE\isLOW.

SRAM_FLASH_WE_B:

outSTD_LOGIC;--SynchronousRead/WriteControlInput（pulleduponPCB）

--AllRead,WriteandDeselectcyclesareinitiatedbytheADVinput.WhentheADVinputisHIGHtheinternal

--burstcounterisincremented.NewexternaladdressescanbeloadedwhenADVisLOW.

SRAM_ADV_LD_B:

outSTD_LOGIC;--SynchronousBurstAddressAdvance/Load（pulleddownonPCB）

SRAM_BW0:

outSTD_LOGIC;--SynchronousByteWriteEnable0（activelow）

SRAM_BW1:

outSTD_LOGIC;--SynchronousByteWriteEnable1（activelow）

SRAM_BW2:

outSTD_LOGIC;--SynchronousByteWriteEnable2（activelow）

SRAM_BW3:

outSTD_LOGIC;--SynchronousByteWriteEnable3（activelow）

--SRAM_FLASH_A0:

outSTD_LOGIC;--notconnectedtoSRAM!

SRAM_FLASH_A1:

outSTD_LOGIC;--SynchronousAddressInput0

SRAM_FLASH_A2:

outSTD_LOGIC;--SynchronousAddressInput1

SRAM_FLASH_A3:

outSTD_LOGIC;

SRAM_FLASH_A4:

outSTD_LOGIC;

SRAM_FLASH_A5:

outSTD_LOGIC;

SRAM_FLASH_A6:

outSTD_LOGIC;

SRAM_FLASH_A7:

outSTD_LOGIC;

SRAM_FLASH_A8:

outSTD_LOGIC;

SRAM_FLASH_A9:

outSTD_LOGIC;

SRAM_FLASH_A10:

outSTD_LOGIC;

SRAM_FLASH_A11:

outSTD_LOGIC;

SRAM_FLASH_A12:

outSTD_LOGIC;

SRAM_FLASH_A13:

outSTD_LOGIC;

SRAM_FLASH_A14:

outSTD_LOGIC;

SRAM_FLASH_A15:

outSTD_LOGIC;

SRAM_FLASH_A16:

outSTD_LOGIC;

SRAM_FLASH_A17:

outSTD_LOGIC;

SRAM_FLASH_A18:

outSTD_LOGIC;

SRAM_FLASH_D0:

inoutSTD_LOGIC;

SRAM_FLASH_D1:

inoutSTD_LOGIC;

SRAM_FLASH_D2:

inoutSTD_LOGIC;

SRAM_FLASH_D3:

inoutSTD_LOGIC;

SRAM_FLASH_D4:

inoutSTD_LOGIC;

SRAM_FLASH_D5:

inoutSTD_LOGIC;

SRAM_FLASH_D6:

inoutSTD_LOGIC;

SRAM_FLASH_D7:

inoutSTD_LOGIC;

SRAM_FLASH_D8:

inoutSTD_LOGIC;

SRAM_FLASH_D9:

inoutSTD_LOGIC;

SRAM_FLASH_D10:

inoutSTD_LOGIC;

SRAM_FLASH_D11:

inoutSTD_LOGIC;

SRAM_FLASH_D12:

inoutSTD_LOGIC;

SRAM_FLASH_D13:

inoutSTD_LOGIC;

SRAM_FLASH_D14:

inoutSTD_LOGIC;

SRAM_FLASH_D15:

inoutSTD_LOGIC;

SRAM_D16:

inoutSTD_LOGIC;

SRAM_D17:

inoutSTD_LOGIC;

SRAM_D18:

inoutSTD_LOGIC;

SRAM_D19:

inoutSTD_LOGIC;

SRAM_D20:

inoutSTD_LOGIC;

SRAM_D21:

inoutSTD_LOGIC;

SRAM_D22:

inoutSTD_LOGIC;

SRAM_D23:

inoutSTD_LOGIC;

SRAM_D24:

inoutSTD_LOGIC;

SRAM_D25:

inoutSTD_LOGIC;

SRAM_D26:

inoutSTD_LOGIC;

SRAM_D27:

inoutSTD_LOGIC;

SRAM_D28:

inoutSTD_LOGIC;

SRAM_D29:

inoutSTD_LOGIC;

SRAM_D30:

inoutSTD_LOGIC;

SRAM_D31:

inoutSTD_LOGIC;

SRAM_DQP0:

inoutSTD_LOGIC;--ParityDataI/O0

SRAM_DQP1:

inoutSTD_LOGIC;--ParityDataI/O1

SRAM_DQP2:

inoutSTD_LOGIC;--ParityDataI/O2

SRAM_DQP3:

inoutSTD_LOGIC;--ParityDataI/O3

wb_adr_i:

instd_logic_vector（17downto0）;

wb_we_i:

instd_logic;

wb_dat_i:

instd_logic_vector（35downto0）;

wb_sel_i:

instd_logic_vector（3downto0）;

wb_dat_o:

outstd_logic_vector（35downto0）;

wb_cyc_i:

instd_logic;

wb_stb_i:

instd_logic;

wb_cti_i:

instd_logic_vector（2downto0）;

wb_bte_i:

instd_logic_vector（1downto0）;

wb_ack_o:

outstd_logic;

wb_err_o:

outstd_logic;

wb_tga_i:

instd_logic:

='0'--'0'tomeanlast（orsingle）4wordsburst

）;

endzbt_top;

architectureBehavioralofzbt_topis

signalZBT_addr,ZBT_addr2:

std_logic_vector（17downto0）;

signalZBT_din,ZBT_din2,ZBT_din1:

std_logic_vector（35downto0）;

signalZBT_dout:

std_logic_vector（35downto0）;

signalBW_enable,SRAM_OE_B2:

std_logic;

signalState:

integer;

constantIDLE:

integer:

=0;

constantC1:

integer:

=1;

constantC2:

integer:

=2;

constantC3:

integer:

=3;

constantC4:

integer:

=4;

constantB1:

integer:

=5;

constantB2:

integer:

=6;

constantB3:

integer:

=7;

constantB4:

integer:

=8;

constantB5:

integer:

=9;

constantB6:

integer:

=10;

constantB4L:

integer:

=11;

constantB5L:

integer:

=12;

constantB6L:

integer:

=13;

constantB0W:

integer:

=14;

constantB1W:

integer:

=15;

constantB2W:

integer:

=16;

constantB3W:

integer:

=17;

constantB4WL:

integer:

=18;

constantB5WL:

integer:

=19;

begin

FSM_State_Control:

process（clk,reset）

begin

if（reset='1'）then

State<=IDLE;

elsif（clk='1'andclk'event）then

caseStateis

whenIDLE=>

if（wb_cyc_i='1'andwb_stb_i='1'）then--startofWBcycle?

if（wb_bte_i/="00"orwb_cti_i/="010"）then--classiccycle

--（WBrule4.25,onlylinearburstsaccepted,WBpermission4.40:

EOB=singleaccess~=sync.classiccycle,WBrule4.10:

unknown=classiccycles）

--wewereinidlestate,soanyclassiccycle,EOBcycleoranycyclewithanonlinearburstisexecutedasaclassicone

State<=C1;

else--Incrementingburstcyclewithlinearbursttype

assert（wb_bte_i="00"andwb_cti_i="010"）report"BadelseonIDLEstate（cti="&integer'image（conv_integer（wb_cti_i））&",bte="&integer'image（conv_integer（wb_bte_i））&"）"severityFAILURE;

if（wb_we_i='0'）then--wbburstread?

State<=B1;

else--wbburstwrite?

State<=B0W;

endif;

endif;

else

State<=IDLE;

endif;

--startsinglewordread/write

whenC1=>

if（wb_cyc_i='1'andwb_stb_i='1'）thenState<=C2;elseState<=IDLE;endif;

whenC2=>--wb_ack<='1'inthiscycle

if（wb_cyc_i='1'andwb_stb_i='1'）thenState<=C3;elseState<=IDLE;endif;

whenC3=>--wb_ack='1'inthiscycle

State<=C4;

whenC4=>

State<=IDLE;

--Burstread

whenB1=>

if（wb_cyc_i='1'andwb_stb_i='1'andwb_cti_i/="111"）thenState<=B2;elseState<=IDLE;endif;

whenB2=>

if（wb_cyc_i='1'andwb_stb_i='1'andwb_cti_i/="111"）thenState<=B3;elseState<=IDLE;endif;

whenB3=>

if（wb_cyc_i='1'andwb_stb_i='1'andwb_cti_i/="111"）then

if（wb_tga_i='0'）then--lastburst?

State<=B4L;

else

State<=B4;

endif;

else

State<=IDLE;

endif;

whenB4=>

if（wb_cyc_i='1'andwb_stb_i='1'andwb_cti_i/="111"）thenState<=B5;elseState<=IDLE;endif;

whenB5=>

if（wb_cyc_i='1'andwb_stb_i='1'andwb_cti_i/="111"）thenState<=B6;elseState<=IDLE;endif;

whenB6=>--gobacktoB3

if（wb_cyc_i='1'andwb_stb_i='1'andwb_cti_i/="111"）thenState<=B3;elseState<=IDLE;endif;

--lastburstread

whenB4L=>

if（wb_cyc_i='1'andwb_stb_i='1'andwb_cti_i/="111"）thenState<=B5L;elseState<=IDLE;endif;

whenB5L=>

if（wb_cyc_i='1'andwb_stb_i='1'andwb_cti_i/="111"）thenState<=B6L;elseState<=IDLE;endif;

whenB6L=>--inthiscyclewb_cti_imustbe111becausetheZBThasaburstlengthof4

State<=IDLE;

--Burstwrite

whenB0W=>

if（wb_cyc_i='1'andwb_stb_i='1'andwb_cti_i/="111"）thenState<=B1W;elseState<=IDLE;endif;

whenB1W=>

if（wb_cyc_i='1'andwb_stb_i='1'andwb_cti_i/="111"）thenState<=B2W;elseState<=IDLE;endif;

whenB2W=>

if（wb_cyc_i='1'andwb_stb_i='1'andwb_cti_i/="111"）thenState<=B3W;elseState<=IDLE;endif;

whenB3W=>

if（wb_cyc_i='1'andwb_stb_i='1'）then--wb_ctishouldbe"111"ifitisthelastburst

if（wb_tga_i='0'）then--lastburst?

State<=B4WL;

else

State<=B0W;

endif;

else

State<=IDLE;

endif;

--lastburstwrite

whenB4WL=