MCS51系列单片机中英文资料对照外文翻译文献综述.docx
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MCS51系列单片机中英文资料对照外文翻译文献综述.docx
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MCS51系列单片机中英文资料对照外文翻译文献综述
MCS-51系列单片机
中英文资料对照外文翻译文献综述
StructureandfunctionoftheMCS-51series
StructureandfunctionoftheMCS-51seriesone-chipcomputerMCS-51isanameofapieceofone-chipcomputerserieswhichIntelCompanyproduces.Thiscompanyintroduced8top-gradeone-chipcomputersofMCS-51seriesin1980afterintroducing8one-chipcomputersofMCS-48seriesin1976.Itbelongtoalotofkindsthislineofone-chipcomputerthechipshave,suchas8051,8031,8751,80C51BH,80C31BH,etc.,theirbasiccomposition,basicperformanceandinstructionsystemareallthesame.8051dailyrepresentatives-51serialone-chipcomputers.
Aone-chipcomputersystemismadeupofseveralfollowingparts:
(1)Onemicroprocessorof8(CPU).
(2)AtslicedatamemoryRAM(128B/256B),itusenotdepositingnotcanreading/datathatwrite,suchasresultnotmiddleofoperation,finalresultanddatawantedtoshow,etc.(3)ProcedurememoryROM/EPROM(4KB/8KB),isusedtopreservetheprocedure,someinitialdataandforminslice.ButdoesnottakeROM/EPROMwithinsomeone-chipcomputers,suchas8031,8032.(4)Four8runsidebysideI/OinterfaceP0fourP3,eachmouthcanuseasintroduction,mayuseasexportingtoo.(5)Twotimer/counter,eachtimer/countermaysetupandcountintheway,usedtocounttotheexternalincident,cansetupintoatimingwaytoo,andcanaccordingtocountorresultoftimingrealizethecontrolofthecomputer.(6)Fivecutoffcuttingoffthecontrolsystemofthesource.(7)OneallduplexserialI/OmouthofUART(universalasynchronousreceiver/transmitter(UART)),isitrealizeone-chipcomputerorone-chipcomputerandserialcommunicationofcomputertousefor.(8)Stretchoscillatorandclockproducecircuit,quartzcrystalfinelytuneelectriccapacityneedouter.Allowoscillationfrequencyas12megahertznowatmost.Everytheabove-mentionedpartwasjoinedthroughtheinsidedatabus.Amongthem,CPUisacoreoftheone-chipcomputer,itisthecontrolofthecomputerandcommandcentre,madeupofsuchpartsasarithmeticunitandcontroller,etc..Thearithmeticunitcancarryon8personsofarithmeticoperationandunitALUoflogicoperationwhileincludingone,the1storingdevicetemporariesof8,storingdevice2temporarily,8'saccumulationdeviceACC,registerBandprocedurestateregisterPSW,etc.PersonwhoaccumulateACCcountby2inputendsenteredofcheckingetc.temporarilyasoneoperationoften,comefrompersonwhostore1operationisitisitmakeoperationtogoontocounttemporarily,operationresultandloopbackACCwithanotherone.Inaddition,ACCisoftenregardedasthetransferstationofdatatransmissionon8051inside.Thesameasgeneralmicroprocessor,itisthebusiestregister.Helprememberingthatagreeingwithaexpressintheorder.Thecontrollerincludestheprocedurecounter,theorderisdeposited,theorderdeciphering,theoscillatorandtimingcircuit,etc.Theprocedurecounterismadeupofcounterof8fortwo,amountsto16.Itisabyteaddresscounteroftheprocedureinfact,thecontentisthenextIAthatwillcarriedoutinPC.Thecontentwhichchangesitcanchangethedirectionthattheprocedurecarriesout.Shakethecircuitin8051one-chipcomputers,onlyneedouterquartzcrystalandfrequencytofinelytunetheelectriccapacity,itsfrequencyrangeisits12MHZof1.2MHZ.Thispulsesignal,as8051basicbeatsofworking,namelytheminimumunitoftime.8051isthesameasothercomputers,theworkinharmonyunderthecontrolofthebasicbeat,justlikeanorchestraaccordingtothebeatplaythatiscommanded.
ThereareROM(procedurememory,canonlyread)andRAMin8051slices(datamemory,canisitcanwrite)twotoread,theyhaveeachindependentmemoryaddressspace,disposewaytobethesamewithgeneralmemoryofcomputer.Procedure8051memoryand8751sliceprocedurememorycapacity4KB,addressbeginfrom0000H,usedforpreservingtheprocedureandformconstant.Data8051-87518031ofmemorydatamemory128B,addressfalse00FH,usingformiddleresulttodepositoperation,thedataarestoredtemporarilyandthedataarebuffered.InRAMofthis128B,thereisunitof32bytesthatcanbeappointedasthejobregister,thisandgeneralmicroprocessorisdifferent,8051sliceRAMandjobregisterrankoneformationthesametoarrangethelocation.ItisnotverythesamethatthememoryofMCS-51seriesone-chipcomputerandgeneralcomputerdisposesthewayinaddition.Generalcomputerforfirstaddressspace,ROMandRAMcanarrangeindifferentspacewithintherangeofthisaddressatwill,namelytheaddressesofROMandRAM,withdistributingdifferentaddressspaceinaformation.Whilevisitingthememory,correspondingandonlyanaddressMemoryunit,canROM,itcanbeRAMtoo,andbyvisitingtheordersimilarly.ThiskindofmemorystructureiscalledthestructureofPrinceton.8051memoriesaredividedintoprocedurememoryspaceanddatamemoryspaceonthephysicsstructure,therearefourmemoryspacesinall:
Theprocedurestoresinoneanddatamemoryspaceoutsidedatamemoryandoneinprocedurememoryspaceandoneoutsideone,thestructureformsofthiskindofproceduredeviceanddatamemoryseparatedformdatamemory,calledHarvardstructure.Butusetheanglefromusers,8051memoryaddressspaceisdividedintothreekinds:
(1)Intheslice,arrangeblocksofFFFFH,0000Hoflocation,inunisonoutsidetheslice(use16addresses).
(2)Thedatamemoryaddressspaceoutsideoneof64KB,theaddressisarrangedfrom0000H64KBFFFFH(with16addresses)tootothelocation.(3)Datamemoryaddressspaceof256B(use8addresses).Threeabove-mentionedmemoryspaceaddressesoverlap,fordistinguishinganddesigningtheordersymbolofdifferentdatatransmissionintheinstructionsystemof8051:
CPUvisitslice,ROMorderspendMOVC,visitblockRAMorderusesMOVXoutsidetheslice,RAMorderusesMOVtovisitinslice.
8051one-chipcomputerhavefour8walkabreastI/Oports,callP0,P1,P2andP3.Eachportis8accuratetwo-waymouths,accountsfor32pinsaltogether.EveryoneI/Olinecanbeusedasintroductionandexportedindependently.Eachportincludesalatch(namelyspecialfunctionregister),oneexportsthedriverandaintroductionbuffer.Makedatacanlatchwhenoutputting,datacanbufferwhenmakingintroduction,butfourfunctionofpassawaytheseself-same.Expandamongthesystemofmemoryoutsidehavingslice,fourportsthesemayserveasaccuratetwo-waymouthofI/Oincommonuse.Expandamongthesystemofmemoryoutsidehavingslice,P2mouthseehigh8addressoff;P0mouthisatwo-waybus,sendtheintroductionof8lowaddressesanddata/exportintimesharing
Thecircuitof8051one-chipcomputersandfourI/Oportsisveryingeniousindesign.FamiliarwithI/Oportlogicalcircuit,notonlyhelptouseportcorrectlyandrationally,andwillinspiretodesigningtheperipherallogicalcircuitofone-chipcomputertosomeextent.Loadabilityandinterfaceofporthavecertainrequirement,becauseoutputgrade,P0ofmouthandP1endoutput,P3ofmouthgradedifferentatstructure,so,theloadabilityandinterfaceofitsdoordemandtohavenothingincommonwitheachother.P0mouthisdifferentfromothermouth,itsoutputgradedrawstheresistancesupremely.Whenusingitasthemouthincommonuse,outputgradeisitleakcircuittoturnon,isiturgeNMOSdrawtheresistanceontakingtobeouterwithitwhileinputtingtogoouttofail.Whenbeingusedasintroduction,shouldwrite"1"toalatchfirst.EveryonewithP0mouthcandrive8ModelLSTTLloadtoexport.P1mouthisanaccuratetwo-waymouthtoo,usedasI/Oincommonuse.DifferentfromP0mouthoutputofcircuitits,drawloadresistancelinkwithpoweroninsidehave.Infact,theresistanceisthattwoeffectsareinchargeofFETandtogether:
OneFETisinchargeofload,itsresistanceisregular.Anotheronecanisitleadtoworkwithcloseattwostate,makeitsPresidentresistancevaluechangeapproximate0orgroupvalueheavytwosituationvery.Whenitis0thattheresistanceisapproximate,candrawthepintothehighlevelfast;whenresistancevalueisverylarge,P1mouthhighelectricityatordinarytimes,canisitdrawelectriccurrentloadtoofferoutwards,drawelectriccurrentloadtoofferoutwards,drawtheresistanceonneedn'tanswerandthinking.Herewhentheportisusedasintroduction,mustwriteinto1tothecorrespondinglatchfirsttoo,makeFETendrelativelyabout20,000ohmsbecauseofloadresistanceinsceneandbecause40,000ohms,willnotexertaninfluenceonthedatathatareinput.ThestructureofP2somemouthissimilartoP0mouth,thereareMUXswitches.Isitsimilartomouthpartlytourge,butmouthlargeaconversioncontrolssomethanP1.P3mouthonemulti-functionalport,mouthgettingmanythanP1ithave"3doorsand4buffers".Twopartsthere,makeherbesidesaccuratetwo-wayfunctionwithP1mouthjust,canalsousethesecondfunctionofeverypin,"and"door3functionsoneswitchinfact,itdeterminestobetooutputdataoflatchtooutputsecondsignaloffunction.ActasW=At1o'clock,outputQendsignal;actasQ=At1o'clock,canoutputWlinesignal.Atthetimeofprogramming,itisthatthefirstfunctionisstillthesecondfunctionbutneedn'thavesoftwarethatsetupP3mouthinadvance.IthardwarenotinsideistheautomatictohavetwofunctionoutputtedwhenCPUcarriesonSFRandseeksthelocationtovisittoP3mouth/atnotlastinglining,thereareinsidehardwarelatchQs=1.TheoperationprincipleofP3mouthissimilartoP1mouth.
Outputgrade,P3ofmouth,P1ofP1,connectwithinsidehave
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