I2C.docx
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- 上传时间:2023-04-30
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- 页数:59
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I2C.docx
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I2C
--i2c.vhd
--Thiscodeimplementsthecontrolofthei2cbuswithaMC68000typeinterface.Itis
--modeledfromtheM-buscomponentincertainMotorolauC.
--TheI2Ccontrolisdoneinthecomponenti2c_controlandtheuCinterfaceisimplemented
--inthecomponentuC_interface.Thisfiledoesnotcontainanylogicdescriptions,itsimply
--instantiatesthetwocomponentsandhooksthemtogether.
libraryIEEE;
useIEEE.std_logic_1164.all;
entityi2cis
generic(I2C_ADDRESS:
std_logic_vector(15downto0):
="0000000000000000");
port(--I2Cbussignals
sda:
inoutstd_logic;
scl:
inoutstd_logic;
--uCinterfacesignals
addr_bus:
instd_logic_vector(23downto0);
data_bus:
inoutstd_logic_vector(7downto0);
as:
instd_logic;--addressstrobe,activelow
ds:
instd_logic;--datastrobe,activelow
r_w:
instd_logic;--read/write
dtack:
outstd_logic;--datatransferacknowledge
irq:
outstd_logic;--interruptrequest
mcf:
inoutstd_logic;--temporaryoutputfortesting
--clockandreset
clk:
instd_logic;--2MHztosupport100KbpsI2Cdatatransferrate.
reset:
instd_logic
);
endi2c;
libraryIEEE;
useIEEE.std_logic_1164.all;
architecturebehaveofi2cis
--*****************************ComponentDefinitions****************************
--DefinetheI2CControllogic
componenti2c_control
port(
--I2Cbussignals
sda:
inoutstd_logic;
scl:
inoutstd_logic;
--interfacesignalsfromuPinterface
txak:
instd_logic;--valueforacknowledgewhenxmit
msta:
instd_logic;--master/slaveselect
msta_rst:
outstd_logic;--resetsMSTAbitifarbitrationislost
rsta:
instd_logic;--repeatedstart
rsta_rst:
outstd_logic;--resetforrepeatedstartbitincontrolregister
mtx:
instd_logic;--masterread/write
mbdr_micro:
instd_logic_vector(7downto0);--uPdatatooutputonI2Cbus
madr:
instd_logic_vector(7downto0);--I2Cslaveaddress
mbb:
outstd_logic;--busbusy
mcf:
inoutstd_logic;--datatransfer
maas:
inoutstd_logic;--addressedasslave
mal:
inoutstd_logic;--arbitrationlost
srw:
inoutstd_logic;--slaveread/write
mif:
outstd_logic;--interruptpending
rxak:
outstd_logic;--receivedacknowledge
mbdr_i2c:
inoutstd_logic_vector(7downto0);--I2CdataforuP
mbcr_wr:
instd_logic;--indicatesthatMCBRregisterwaswritten
mif_bit_reset:
instd_logic;--indicatesthattheMIFbitshouldbereset
mal_bit_reset:
instd_logic;--indicatesthattheMALbitshouldbereset
sys_clk:
instd_logic;
reset:
instd_logic);
endcomponent;
--DefinetheuCinterface
componentuc_interface
generic(UC_ADDRESS:
std_logic_vector(15downto0):
="0000000000000000");
port(--68000parallelbusinterface
clk:
inSTD_LOGIC;
reset:
inSTD_LOGIC;
addr_bus:
inSTD_LOGIC_VECTOR(23downto0);
data_bus:
inoutSTD_LOGIC_VECTOR(7downto0);
as:
inSTD_LOGIC;--Addressstrobe,activelow
ds:
inSTD_LOGIC;--Datastrobe,activelow
--Directionalpins
r_w:
inSTD_LOGIC;--Activelowwrite,
--activehighread
dtack:
outSTD_LOGIC;--Datatransferacknowledge
irq:
outSTD_LOGIC;--Interruptrequest
--InternalI2CBusRegisters
--AddressRegister(Containsslaveaddress)
Madr:
inoutSTD_LOGIC_VECTOR(7downto0);
--ControlRegister
men:
inoutSTD_LOGIC;--I2CEnablebit
mien:
inoutSTD_LOGIC;--interruptenable
msta:
inoutSTD_LOGIC;--Master/Slavebit
mtx:
inoutSTD_LOGIC;--Masterread/write
txak:
inoutSTD_LOGIC;--acknowledgebit
rsta:
inoutSTD_LOGIC;--repeatedstart
mbcr_wr:
outSTD_LOGIC;--indicatesthatthecontrolreghasbeenwrittenrsta_rst:
inSTD_LOGIC;--resetforrepeatedstartbitincontrolregister
--StatusRegister
mcf:
inSTD_LOGIC;--endofdatatransfer
maas:
inSTD_LOGIC;--addressedasslave
mbb:
inSTD_LOGIC;--busbusy
mal:
inSTD_LOGIC;--arbitrationlost
srw:
inSTD_LOGIC;--slaveread/write
mif:
inSTD_LOGIC;--interruptpending
rxak:
inSTD_LOGIC;--receivedacknowledge
mal_bit_reset:
outSTD_LOGIC;--indicatesthattheMALbitshouldbereset
mif_bit_reset:
outSTD_LOGIC;--indicatesthattheMIFbitshouldbereset
msta_rst:
inSTD_LOGIC;--resetstheMSTAbitifarbitrationislost
--DataRegister
mbdr_micro:
inoutSTD_LOGIC_VECTOR(7downto0);
mbdr_i2c:
inSTD_LOGIC_VECTOR(7downto0);
mbdr_read:
outSTD_LOGIC
);
endcomponent;
--******************************SignalDeclarations****************************
--controlregister
signalmadr:
std_logic_vector(7downto0);--I2Caddress
signalmen:
std_logic;--i2cenable-usedasi2creset
signalmien:
std_logic;--interruptenable
signalmsta:
std_logic;--i2cmaster/slaveselect
signalmtx:
std_logic;--masterread/write
signaltxak:
std_logic;--valueofacknowledgetobetransmitted
signalrsta:
std_logic;--generatearepeatedstart
signalrsta_rst:
std_logic;--resetforrepeatedstartbit
signalmbcr_wr:
std_logic;--indicatestheuChaswrittentheMBCR
--statusregister
--signalmcf:
std_logic;--indicatesacompleteddatabytetransfer
signalmaas:
std_logic;--indicatesthechiphasbeenaddressedasI2cslave
signalmbb:
std_logic;--indicatesthei2cbusisbusy
signalmal:
std_logic;--indicatesthatarbitrationforthei2cbusislost
signalsrw:
std_logic;--slaveread/write
signalmif:
std_logic;--interruptpending
signalrxak:
std_logic;--valueofreceivedacknowledge
--resetsforcertainstatusandcontrolregisterbits
signalmal_bit_reset:
std_logic;--resetsarbitrationlostindicator
signalmif_bit_reset:
std_logic;--resetsinterruptpendingbit
signalmsta_rst:
std_logic;--resetsmaster/slaveselectwhenarbitrationislost
--dataregisters
--therearetwodataregisters,onetoholdtheuCdatawhenthechipistransmittingonI2C
--andonetoholdtheI2Cdatawhenthechipisreceiving.Thisallowsthetworegistersto
--beclockedbydifferentclocks
signalmbdr_micro:
std_logic_vector(7downto0);--uCdataregister
signalmbdr_i2c:
std_logic_vector(7downto0);--i2cdataregister
signalmbdr_read:
std_logic;--indicatesthembdr_i2cregisterhasbeen
--readbytheuC
begin
--*****************************ComponentInstantiations***************************
--InstantiatetheI2CControllerandconnectit
I2C_CTRL:
i2c_control
portmap(
--I2Cbussignals
sda=>sda,
scl=>scl,
--interfacesignalsfromuPinterface
txak=>txak,
msta=>msta,
msta_rst=>msta_rst,
rsta=>rsta,
rsta_rst=>rsta_rst,
mtx=>mtx,
mbdr_micro=>mbdr_micro,
madr=>madr,
mbb=>mbb,
mcf=>mcf,
maas=>maas,
mal=>mal,
srw=>srw,
mif=>mif,
rxak=>rxak,
mbdr_i2c=>mbdr_i2c,
mbcr_wr=>mbcr_wr,
mif_bit_reset=>mif_bit_reset,
mal_bit_reset=>mal_bit_reset,
sys_clk=>clk,
reset=>men
);
--InstantiatetheuCinterfaceandconnectit
uC_CTRL:
uc_interface
genericmap(UC_ADDRESS=>I2C_ADDRESS)
portmap(
--68000parallelbusinterface
clk=>clk,
reset=>reset,
addr_bus=>addr_bus,
data_bus=>data_bus,
as=>as,
ds=>ds,
--Directionalpins
r_w=>r_w,
dtack=>dtack,
irq=>irq,
--InternalI2CBusRegisters
--AddressRegister(Containsslaveaddress)
madr=>madr,
--ControlRegister
men=>men,
mien=>mien,
msta=>msta,
mtx=>mtx,
txak=>txak,
rsta=>rsta,
mbcr_wr=>mbcr_wr,
rsta_rst=>rsta_rst,
--StatusRegister
mcf=>mcf,
maas=>maas,
mbb=>mbb,
mal=>mal,
srw=>srw,
mif=>mif,
rxak=>rxak,
mal_bit_reset=>mal_bit_reset,
mif_bit_reset=>mif_bit_reset,
msta_rst=>msta_rst,
--DataRegister
mbdr_micro=>mbdr_micro,
mbdr_i2c=>mbdr_i2c,
mbdr_read=>mbdr_read
);
endbehave;
--i2c_control.vhd
--Thiscodeimplementsthecontrolofthei2cbus
--createdfromcodedeveloped6/99-mademinorchanges
--toreducemacrocellcountsandchangedsystemclockto2Mhz
--clockcountonlyneedstobefourbitssinceonlycountshalf
--clockperiods
libraryIEEE;
useIEEE.std_logic_1164.all;
useIEEE.std_logic_arith.all;
entityi2c_controlis
port(
--I2Cbussignals
sda:
inoutstd_logic;
scl:
inoutstd_logic;
--interfacesignalsfromuPinterface
txak:
instd_logic;--valueforacknowledgewhenxmit
msta:
instd_logic;--master/slaveselect
msta_rst:
outstd_logic;--resetsMSTAbitifarbitrationislost
rsta:
instd_logic;--repeatedstart
rsta_rst:
outstd_logic;--repeatedstartreset
mtx:
instd_logic;--masterread/write
mbdr_micro:
instd_logic_vector(7downto0);--uPdatatooutputonI2Cbus
madr:
instd_logic_vector(7downto0);--I2Cslaveaddress
mbb:
outstd_logic;--busbusy
mcf:
inoutstd_logic;--datatransfer
maas:
inoutstd_logic;--addressedasslave
mal:
inoutstd_logic;--arbitrationlost
srw:
inoutstd_logic;--slaveread/write
mif:
outstd_logic;--interruptpending
rxak:
outstd_logic;--receivedacknowledge
mbdr_i2c:
inoutstd_logic_vector(7downto0);--I2CdataforuP
mbcr_wr:
instd_logic;--indicatesthatMCBRregisterwaswritten
mif_bit_reset:
instd_logic;--indicatesthattheMIFbitshouldbereset
mal_bit_reset:
instd_logic;--indicatesthattheMALbitshouldbereset
sys_clk:
instd_logic;
reset:
instd_logic);
endi2c_control;
lib
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- 关 键 词:
- I2C
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