外文翻译排版格式参考Word文档下载推荐.docx
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姓名:
张杨
学号:
B10030942
外文出处:
附件:
1.原文;
2.译文
2014年03月
AnIntroductiontotheARM7Architecture
TrevorMartinCEng,MIEE
TechnicalDirector
ThisarticlegivesanoverviewoftheARM7architectureandadescriptionofitsmajorfeaturesforadevelopernewtothedevice.FuturearticleswillexamineotheraspectsoftheARMarchitecture.
BasicCharacteristics
TheprinciplefeatureoftheARM7microcontrolleristhatitisaregisterbasedload-and-storearchitecturewithanumberofoperatingmodes.WhiletheARM7isa32bitmicrocontroller,itisalsocapableofrunninga16-bitinstructionset,knownas"
THUMB"
.Thishelpsitachieveagreatercodedensityandenhancedpowersaving.Whilealloftheregister-to-registerdataprocessinginstructionsaresingle-cycle,otherinstructionssuchasdatatransferinstructions,aremulti-cycle.Toincreasetheperformanceoftheseinstructions,theARM7hasathree-stagepipeline.Duetotheinherentsimplicityofthedesignandlowgatecount,ARM7istheindustryleaderinlow-powerprocessingonawattsperMIPbasis.Finally,toassistthedeveloper,theARMcorehasabuilt-inJTAGdebugportandon-chip"
embeddedICE"
thatallowsprogramstobedownloadedandfullydebuggedin-system.
InordertokeeptheARM7bothsimpleandcost-effective,thecodeanddataregionsareaccessedviaasingledatabus.ThuswhiletheARM7iscapableofsingle-cycleexecutionofalldataprocessinginstructions,datatransferinstructionsmaytakeseveralcyclessincetheywillrequireatleasttwoaccessesontothebus(onefortheinstructiononeforthedata).Inordertoimproveperformance,athreestagepipelineisusedthatallowsmultipleinstructionstobeprocessedsimultaneously.
Thepipelinehasthreestages;
FETCH,DECODEandEXECUTE.Thehardwareofeachstageisdesignedtobeindependentsouptothreeinstructionscanbeprocessedsimultaneously.Thepipelineismosteffectiveinspeedingupsequentialcode.Howeverabranchinstructionwillcausethepipelinetobeflushedmarringitsperformance.AsweshallseelatertheARM7designershadsomecleverideastosolvethisproblem.
Fig1ARM3-Stagepipeline
ARM7ProgrammingModel
Theprogrammer'
smodeloftheARM7consistsof15userregisters,asshowninFig.3,withR15beingusedastheProgramCounter(PC).SincetheARM7isaload-and-storearchitecture,anuserprogrammustloaddatafrommemoryintotheCPUregisters,processthisdataandthenstoretheresultbackintomemory.Unlikeotherprocessorsnomemorytomemoryinstructionsareavailable.
Fig2LoadAndStoreArchitecture
AsstatedaboveR15istheProgramCounter.R13andR14alsohavespecialfunctions;
R13isusedasthestackpointer,thoughthishasonlybeendefinedasaprogrammingconvention.UnusuallytheARMinstructionsetdoesnothavePUSHandPOPinstructionssostackhandlingisdoneviaasetofinstructionsthatallowloadingandstoringofmultipleregistersinasingleoperation.ThusitispossibletoPUSHorPOPtheentireregistersetontothestackinasingleinstruction.R14hasspecialsignificanceandiscalledthe"
linkregister"
.Whenacallismadetoaprocedure,thereturnaddressisautomaticallyplacedintoR14,ratherthanontoastack,asmightbeexpected.AreturncanthenbeimplementedbymovingthecontentsofR14intoR15,thePC.Formultiplecallingtrees,thecontentsofR14(thelinkregister)mustbeplacedontothestack.
Fig3UserModeRegisterModel
Inadditiontothe16CPUregisters,thereisacurrentprogramstatusregister(CPSR).Thiscontainsasetofconditioncodeflagsintheupperfourbitsthatrecordtheresultofapreviousinstruction,asshowninFig4.Inadditiontotheconditioncodeflags,theCPSRcontainsanumberofuser-configurablebitsthatcanbeusedtochangetheprocessormode,enterThumbprocessingandenable/disableinterrupts.
Fig4CurrentProgramStatusRegisterandFlags
ExceptionAndInterruptModes
TheARM7architecturehasatotalofsixdifferentoperatingmodes,asshownbelow.Thesemodesareprotectedorexceptionmodeswhichhaveassociatedinterruptsourcesandtheirownregistersets.
User:
Thismodeisusedtoruntheapplicationcode.OnceinusermodetheCPSRcannotbewrittentoandmodescanonlybechangedwhenanexceptionisgenerated.
FIQ:
(FastInterruptreQuest)Thissupportshighspeedinterrupthandling.Generallyitisusedforasinglecriticalinterruptsourceinasystem
IRQ:
(InterruptReQuest)Thissupportsallotherinterruptsourcesinasystem
Supervisor:
A"
protected"
modeforrunningsystemlevelcodetoaccesshardwareorrunOScalls.TheARM7entersthismodeafterreset
Abort:
Ifaninstructionordataisfetchedfromaninvalidmemoryregion,anabortexceptionwillbegenerated
UndefinedInstruction:
IfaFETCHEDopcodeisnotanARMinstruction,anundefinedinstructionexceptionwillbegenerated.
TheUserregistersR0-R7arecommontoalloperatingmodes.HoweverFIQmodehasitsownR8-R14thatreplacetheuserregisterswhenFIQisentered.Similarly,eachoftheothermodeshavetheirownR13andR14sothateachoperatingmodehasitsownuniqueStackpointerandLinkregister.TheCPSRisalsocommontoallmodes.Howeverineachoftheexceptionmodes,anadditionalregister一thesavedprogramstatusregister(SPSR),isadded.WhentheprocessorchangesthecurrentvalueoftheCPSRstoredintheSPSR,thiscanberestoredonexitingtheexceptionmode.
Fig5FullRegisterSetForARM7
EntrytotheExceptionmodesisthroughtheinterruptvectortable.ExceptionsintheARMprocessorcanbesplitintothreedistincttypes.
(i)Exceptionscausedbyexecutinganinstruction,theseincludesoftwareinterrupts,undefinedinstructionexceptionsandmemoryabortexceptions
(ii)Exceptionscausedasasideeffectofaninstructionsuchasaabortcausedbytryingtofetchdatafromaninvalidmemoryregion.
(iii)Exceptionsunrelatedtoinstructionexecution,thisincludesreset,FIQandIRQinterrupts.
Ineachcaseentryintotheexceptionmodeusesthesamemechanism.Ongenerationoftheexception,theprocessorswitchestotheprivilegedmode,thecurrentvalueofthePC+4issavedintotheLinkregister(R14)oftheprivilegedmodeandthecurrentvalueofCPSRissavedintotheprivilegedmode'
sSPSR.TheIRQinterruptsarealsodisabledandiftheFIQmodeisentered,theFIQinterruptsarealsodisabled,FinallytheProgramCounterisforcedtotheexceptionvectoraddressandprocessingoftheexceptioncanstart.Usuallythefirstactionoftheexceptionroutinewillbetopushsomeoralloftheuserregistersontothestack.
Fig6ARM7VectorTable
Acoupleofthingsareworthnotingonthevectortable.Firstly,thereisamissingvectorat0x000000014.ThiswasusedonanearlierARMarchitectureandisleftemptyonARM7toallowbackwardcompatibility.Secondly,theFIQinterruptisatthehighestaddresssotheFIQroutinescouldstartfromthisaddress,removingtheneedforajumpinstructiontoreachtheroutine.IthelpsmakeentryintotheFIQroutineasfastaspossible.
Onceprocessingoftheexceptionhasfinished,theprocessorcanleavetheprivilegedmodeandreturntotheusermode.Firstlythecontentsofanyregisterspreviouslysavedontothestackmustberestored.NexttheCSPRmustberestoredfromtheSPSRandfinallytheProgramCounterisrestoredbymovingthecontentsofthelinkregistertoR15,(i.e.theProgramCounter).Theinterruptedprogramflowcanthenrestart.
DataTypes
TheARMinstructionsetsupportssixdatatypesnamely8bitsignedandunsigned,16bitsignedandunsignedplus32bitsignedandunsigned.TheARMprocessorinstructionsethasbeendesignedtosupportthesedatatypesinLittleorBig-endianformats.HowevermostARMsiliconimplementationsusetheLittle-endianformat.
ARMinstructionstypicallyhaveathree-operandformat,asshownbelow
ADDRl,R2,R3;
Rl=R2+R3
ARM7ProgramFlowControl
Inallprocessorsthereisasmallgroupofinstructionsthatareconditionallyexecuteddependingonagroupofprocessorflags.Thesearebranchinstructionssuchasbranchnotequal.WithintheARMinstructionset,allinstructionsareconditionallyexecutable.
Fig.7InstructionConditionCodeBits
Thetopfourbitsofeachinstructioncontainaconditioncodethatmustbesatisfiediftheinstructionistobeexecuted.Thisgoesalongwaytoeliminatingsmallbranchesintheprogramcodeandeliminatingstallsinthepipelinesoincreasingtheoverallprogramperformance.Thusforsmallconditionalbranchesofthreeinstructionsorless,conditionalexecutionofinstructionsshouldbeused.Forlargerjumps,normalbranchinginstructionsshouldbeused.
Fig.8InstructionConditionCodes
ThusourADDinstructionbelowcouldbeprefixedwithaconditioncode,asshown.Thisaddsnooverheadtoinstructionexecution
EQADDR1,R2,R3;
If(Zeroflag=1)thenR1=R2+R3
TheARM7processoralsohasa32-bitbarrelshifterthatallowsittoshiftorrotateoneoftheoperandsinadataprocessinginstruction.Thistakesplaceinthesamecycleastheinstruction.TheADDinstructioncouldbeexpandedasfollows
EQADDR1,R2R3,LSL#2;
If(Zeroflag=1)thenR1=R2+(R3x4)
FinallytheprogrammermaydecideifaparticularinstructioncansettheconditioncodeflagsintheCPSR.
EQADDSR1,R2R3,LSL#2;
If(Zeroflag=1)thenR1=R2+(R3x4)andsetconditioncodeflags
IntheARMinstructionsettherearenodedicatedcallorreturninstructions.Insteadthesefunctionsarecreatedoutofasmallgroupofbranchinginstructions.
Thestandardbranch(B)instructionall
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