完整版51单片机外文文献Word格式.docx
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完整版51单片机外文文献Word格式.docx
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Port0
Port0isan8-bitopen-drainbi-directionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashigh-impedanceinputs.Port0mayalsobeconfiguredtobethemultiplexedaddress/databusduringaccessestoexternalprogramanddatamemory.InthismodeP0hasinternalPull-upresistor.Port0alsoreceivesthecodebytesduringFlashprogramming,andoutputsthecodebytesduringProgramverification.ExternalPull-upresistorsarerequiredduringProgramverification.
Port1
Port1isan8-bitbi-directionalI/OportwithinternalPull-upresistors.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pinstheyarepulledhighbytheinternalPull-upresistorsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalPull-upresistors.Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.
Port2
Port2isan8-bitbi-directionalI/OportwithinternalPull-upresistor.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pinstheyarepulledhighbytheinternalPull-upresistorandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent,becauseoftheinternalPull-upresistor.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses.Inthisapplication,itusesstronginternalPull-upresistorwhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses,Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.
Port3
Port3isan8-bitbi-directionalI/OportwithinternalPull-upresistor.ThePort3
outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pinstheyarepulledhighbytheinternalPull-upresistorandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthePull-upresistor.Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89C51aslistedbelow:
PortPin
AUernateFunctions
P3.0
RXD(serialinputpert)
P3.1
TXD(serialoutputport)
P3.2
IMTO(externalinterrupt0)
P3.3
INIT1(externalinterrupt1)
P3,4
TO(timeroexternalinput)
P3,5
T1(timer1externalinput)
P3,6
VVR(externaldatamennorywritestrobe)
P3.7
RDt@Kt&
rnaldatamemoryr&
adstrobe)
Port3alsoreceivessomecontrolsignalsforFlashprogrammingandverification.
RST
Resetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.
ALE/PROG
AddressLatchEnableoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput(PROG)duringFlashprogramming.InnormaloperationALEisemittedataconstantrateof1/6theoscillatorfrequency,andmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskippedduringeachaccesstoexternalDataMemory.
Ifdesired,ALEoperationcanbedisabledbysettingbit0ofSFRlocation8EH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledhigh.SettingtheALE-disablebithasnoeffectifthemicrocontrollerisinexternalexecutionmode.
PSEN
ProgramStoreEnableisthereadstrobetoexternalprogrammemory.WhentheAT89C51isexecutingcodefromexternalprogrammemory,PSENisactivatedtwiceeachmachinecycle,exceptthattwoPSENactivationsareskippedduringeachaccesstoexternaldatamemory.
EA/VPP
ExternalAccessEnable.EAmustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFH.Note,however,thatiflockbit1isprogrammed,EAwillbeinternallylatchedonreset.EAshouldbestrappedtoVCCforinternalprogramexecutions.Thispinalsoreceivesthe12-voltprogrammingenablevoltage(VPP)duringFlashprogramming,forpartsthatrequire12-voltVPP.
XTAL1
Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit.
XTAL2
Outputfromtheinvertingoscillatoramplifier.
OscillatorCharacteristics
XTAL1andXTAL2aretheinputandoutput,respectively,ofaninvertingamplifierwhichcanbeconfiguredforuseasanon-chiposcillator,asshowninFigure1.Eitheraquartzcrystalorceramicresonatormaybeused.Todrivethedevicefromanexternalclocksource,XTAL2shouldbeleftunconnectedwhileXTAL1isdrivenas
showninFigure2.Therearenorequirementsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclockingcircuitryisthroughadivide-by-twoflip-flop,butminimumandmaximumvoltagehighandlowtimespecificationsmustbeobserved.
ftND
GND
Configuration
IdleMode
Inidlemode,theCPUputsitselftosleepwhilealltheonchipperipheralsremainactive.Themodeisinvokedbysoftware.Thecontentoftheon-chipRAMandallthespecialfunctionsregistersremainunchangedduringthismode.Theidlemodecanbeterminatedbyanyenabledinterruptorbyahardwarereset.Itshouldbenotedthatwhenidleisterminatedbyahardwarereset,thedevicenormallyresumesprogramexecution,fromwhereitleftoff,uptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrol.On-chiphardwareinhibitsaccesstointernalRAMinthisevent,butaccesstotheportpinsisnotinhibited.ToeliminatethepossibilityofanunexpectedwritetoaportpinwhenIdleisterminatedbyreset,theinstructionfollowingtheonethatinvokesIdleshouldnotbeonethatwritestoaportpinortoexternalmemory.
Power-downMode
Inthepower-downmode,theoscillatorisstopped,andtheinstructionthatinvokespower-downisthelastinstructionexecuted.Theon-chipRAMandSpecialFunctionRegistersretaintheirvaluesuntilthepower-downmodeisterminated.Theonlyexitfrompower-downisahardwarereset.ResetredefinestheSFRsbutdoesnotchangetheon-chipRAM.TheresetshouldnotbeactivatedbeforeVCCisrestoredtoitsnormaloperatinglevelandmustbeheldactivelongenoughtoallowtheoscillatortorestartandstabilize.
StatusofExternalPinsDu和ngIdleandPower-downModes
Mode
ALE
PORTO
PORI1
POAT2
PORT3
idiQ
1nt«
rnal
1
Data
hk?
External
Fleet
Address
Pzwer-dswn
Internal
D
缶饲
□ala
Pcwordown
Exiornsil
冋aal
Daia
ProgramMemoryLockBits
Onthechiparethreelockbitswhichcanbeleftunprogrammed(U)orcanbe
programmed(P)toobtaintheadditionalfeatureslistedinthetablebelow.
LockBitProtectionModes
PragrairLockP愣
ProlvdlonType
LB1
LB2
心
u
U
Noproq-amlodetenures
2
P
MOVCinstruclionsexecutedlfrotriexlerndprogrammemoryar&
disabledfrom(etctiirtgcotkby値离ioninlArrnlmfiinory,rS話sarnplrdandilat:
hAdon^ndFuitherpro勺序inking.)flh$Flashdialed
3
Sameasm&
do2.alsov^rlyis
A
p
Sameasmode3.al»
oexternalexecut-oni:
.dibbled
Whenlockbit1isprogrammed,thelogiclevelattheEApinissampledandlatchedduringreset.Ifthedeviceispoweredupwithoutareset,thelatchinitializestoarandomvalue,andholdsthatvalueuntilresetisactivated.ItisnecessarythatthelatchedvalueofEAbeinagreementwiththecurrentlogiclevelatthatpininorderforthedevicetofunctionproperly.
译文:
AT89C51的介绍
描述
AT89C51是一个低电压,高性能CMOS8位单片机带有4K字节的可反复擦写的程序存储器(PENROM。
这种器件采用ATMEL公司的高密度、不容易丢失存储技术生产,并且能够与MCS51系列的单片机兼容。
片内含有8位中央处理器
和闪烁存储单元,有较强的功能的AT89C51单片机能够被应用到控制领域中。
功能特性
AT89C51提供以下的功能标准:
4K字节闪烁存储器,128字节随机存取数据存储器,32个I/O口,2个16位定时/计数器,1个5向量两级中断结构,1个串行通信口,片内震荡器和时钟电路。
另外,AT89C51还可以进行OHZ的静态逻辑操作,并支持两种软件的节电模式。
闲散方式停止中央处理器的工作,能够允许随机存取数据存储器、定时/计数器、串行通信口及中断系统继续工作。
掉电方式保存随机存取数据存储器中的内容,但震荡器停止工作并禁止其它所有部件的工作直到下一个复位。
引脚描述
VCC电源电压
GND:
地
P0口
P0口是一组8位漏极开路双向I/O口,即地址/数据总线复用口。
作为输出口时,每一个管脚都能够驱动8个TTL电路。
当“1被写入P0口时,每个管脚都能够作为高阻抗输入端。
P0口还能够在访问外部数据存储器或程序存储器时,转换地址和数据总线复用,并在这时激活内部的上拉电阻。
P0口在闪
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