verilog上机练习一二参考程序Word格式文档下载.docx
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verilog上机练习一二参考程序Word格式文档下载.docx
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//----------?
?
(?
)?
-------------------------
`timescale1ns/1ns//?
`include"
./mu4_1.v"
//?
//?
moduletest_mu4_1;
reg[3:
0]sin4_test;
reg[1:
0]select_test;
regclock;
wireout1_test;
initial//initial?
begin
sin4_test=4'
b0000;
select_test=2'
b00;
clock=0;
end
always#50clock=~clock;
always@(posedgeclock)//?
a?
b
sin4_test={$random}%4;
a?
0?
1?
initial
#20000select_test=2'
b01;
b10;
b11;
end//?
begin#100000$stop;
mu4_1m(.s_in4(sin4_test),.select(select_test),.out_1(out1_test));
t.m
endmodule
2.比较器(比较大于,小于,等于)
modulecompare_sbe(small_out,big_out,equal_out,a,b);
inputa,b;
outputequal_out,small_out,big_out;
assignequal_out=(a==b)?
1:
0;
assignbig_out=(a>
b)?
assignsmall_out=(a<
//-------------------------------------------------------------
//----------?
./compare_sbe.v"
modulecompare_sbe_test;
rega_test,b_test;
wireequal_out,small_out,big_out;
a_test=0;
b_test=0;
#100a_test=0;
b_test=1;
#100a_test=1;
#100$stop;
compare_sbem(.small_out(small_out),.big_out(big_out),.equal_out(equal_out),.a(a_test),.b(b_test));
3.编码器
(1)模块程序
modulecode8_3(indata8,outdata3);
input[7:
0]indata8;
output[2:
0]outdata3;
reg[2:
always@(indata8)
case(indata8)
8'
b0000_0001:
outdata3=3'
d0;
b0000_0010:
d1;
b0000_0100:
d2;
b0000_1000:
d3;
b0001_0000:
d4;
b0010_0000:
d5;
b0100_0000:
d6;
b1000_0000:
d7;
(2)测试程序
./code8_3.v"
modulecode8_3_test;
reg[7:
wire[2:
0]outcode3;
#100indata8=8'
b0000_0001;
b0000_0010;
b0000_0100;
b0000_1000;
b0001_0000;
b0010_0000;
b0100_0000;
b1000_0000;
b1100_0100;
b1100_0101;
code8_3m(.indata8(indata8),.outdata3(outcode3));
4.译码器
moduledecode3_8(indata3,outdata8);
input[2:
0]indata3;
output[7:
0]outdata8;
reg[7:
always@(indata3)
case(indata3)
3'
d0:
outdata8=8'
d1:
d2:
d3:
d4:
d5:
d6:
d7:
b0000_0000;
./decode3_8.v"
moduledecode3_8_test;
reg[2:
wire[7:
0]outcode8;
#100indata3=3'
decode3_8m(.indata3(indata3),.outdata8(outcode8));
5.触发器
moduledbuff(d,clk,en,rst,q);
inputd,clk,en,rst;
outputq;
regq;
always@(posedgeclkornegedgerst)
if(!
rst)
begin
q<
=0;
else
if(!
en)
begin
q<
end
else
=d;
./dbuff.v"
moduledbuff_test;
regd_test,clk_test,en_test,rst_test;
wireq_test;
d_test=1'
b0;
clk_test=1'
en_test=1'
rst_test=1'
always@(posedgeclock)
clk_test=~clk_test;
#1d_test={$random}%2;
#100rst_test=1'
b1;
#200rst_test=1'
#1000en_test=1'
dbuffm(.d(d_test),.clk(clk_test),.en(en_test),.rst(rst_test),.q(q_test));
6.移位寄存器
moduleshift_buff(indata1,clk,rst,outdata8);
inputindata1,clk,rst;
outdata8<
=8'
outdata8=outdata8<
<
1;
outdata8[0]=indata1;
./shift_buff.v"
moduleshift_test;
regindata1_test,clk_test,rst_test;
0]outdata8_test;
indata1_test=1'
#1indata1_test={$random}%2;
shift_buffm(.indata1(indata1_test),.clk(clk_test),.rst(rst_test),.outdata8(outdata8_test));
7.计数器
modulecounter4(load_data,rst,clk,load,count_data,cin);
inputclk,rst,load;
0]load_data;
output[3:
0]count_data;
outputcin;
reg[3:
regcin;
count_data<
cin<
if(load)
=load_data;
if(count_data==4'
hf)
=1;
=count_data+1;
./counter4.v"
modulecounter4_test;
regclk_test,rst_test,load_test,clock;
0]load_data_test;
wire[3:
0]count_data_test;
wirecin_test;
initial//initial?
begin
load_data_test=4'
b1101;
load_test=1'
rst_test=0;
clk_test=0;
clock=0;
always#50clock=~clock;
always@(posedgeclock)
initial
#100rst_test=1'
#200rst_test=1'
#100load_test=1'
#200load_test=1'
end//?
begin#100000$stop;
counter4m(.load_data(load_data_test),.rst(rst_test),.clk(clk_test),.load(load_test),.count_data(count_data_test),.cin(cin_test));
8.分频器
moduleclk10_div(clk10,rst,clk1);
inputclk10,rst;
outputclk1;
regclk1;
0]count;
always@(posedgeclk10ornegedgerst)
if(!
clk1<
count<
else
if(count==3'
d4)
=~clk1;
=count+1;
./clk10_div.v"
moduleclk10_div_test;
regclk10_test,rst_test;
regclock;
wireclk1_test;
clk10_test=1'
clk10_test=~clk10_test;
clk10_divm(.clk10(clk10_test),.rst(rst_test),.clk1(clk1_test));
9.指令译码器
modulecode_cal(data_a,data_b,out_data,oprate);
0]data_a,data_b;
0]oprate;
0]out_data;
parameterplus=0,minus=1,band=2,bor=3,unegate=4;
always@(oprate,data_a,data_b)
case(oprate)
plus:
out_data=data_a+data_b;
minus:
out_data=data_a-data_b;
band:
out_data=data_a&
data_b;
bor:
out_data=data_a|data_b;
unegate:
out_data=~data_a;
out_data=3'
./code_cal.v"
modulecode_cal_test;
0]data_a_test,data_b_test;
0]oprate_test
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