FPGA数字时钟verilogWord下载.docx
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- 上传时间:2023-02-03
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FPGA数字时钟verilogWord下载.docx
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b1;
else
end
jishu_1ms<
=16'
elseif(jishu_1ms<
cnt_1ms)
=jishu_1ms+1'
assignen_1s=(jishu_1s==cnt_1s)?
1'
b1:
//1s
assignen_1ms=(jishu_1ms==cnt_1ms)?
//1ms
endmodule
//按键控制部分
moduleanjian(clk,rst_n,key1,key2,key1_low,key2_low);
inputkey1;
//分加
inputkey2;
//分减
outputkey1_low;
//按键按下消抖后的标志位
outputkey2_low;
regreg0_key;
//key1消抖
regreg1_key;
regreg2_key;
//key2消抖
regreg3_key;
always@(posedgeclkornegedgerst_n)
reg0_key<
=1'
reg1_key<
=key1;
=reg0_key;
//根据非阻塞赋值的原理,reg1_key存储的值是reg0_key上一个时钟的值
//脉冲边沿检测法,当寄存器key1由1变为0时,key1_an的值变为高,维持一个时钟周期
wirekey1_an;
assignkey1_an=reg1_key&
(~reg0_key);
reg2_key<
reg3_key<
=key2;
=reg2_key;
//脉冲边沿检测法,当寄存器key2由1变为0时,key2_an的值变为高,维持一个时钟周期
wirekey2_an;
assignkey2_an=reg3_key&
(~reg2_key);
reg[19:
0]cnt_key1;
//计数寄存器
always@(posedgeclkornegedgerst_n)
if(!
cnt_key1<
=20'
d0;
//异步复位
elseif(key1_an)
=20'
//led1_an=1,按键确认按下,cnt_key1从0开始计数else
=cnt_key1+1'
0]cnt_key2;
cnt_key2<
elseif(key2_an)
=cnt_key2+1'
//以下为消抖程序
regreg_low;
regreg1_low;
reg_low<
elseif(cnt_key1==20'
hfffff)//时钟50mhz的话大约计时是20ms
//led_an=1,按键确认按下,cnt_key从0开始计数,这时候还有消抖动,计数20ms后抖动滤除了此时再锁存一下key1的值
end//这时key1的值就稳定了
reg1_low<
=reg_low;
assignkey1_low=reg1_low&
(~reg_low);
//当寄存器reg_low由1变为0时,key_low的值变为高,维持一个时钟周期
regreg2_low;
regreg3_low;
reg2_low<
elseif(cnt_key2==20'
hfffff)
reg3_low<
=reg2_low;
assignkey2_low=reg3_low&
(~reg2_low);
//时、分、秒
moduleshijian(clk,rst_n,en_1s,key1_low,key2_low,shi,fen,miao);
inputen_1s;
inputkey1_low;
inputkey2_low;
output[5:
0]shi;
0]fen;
0]miao;
reg[5:
always@(posedgeclkornegedgerst_n)begin
shi<
=6'
fen<
miao<
elseif(en_1s)
miao=miao+1'
if(miao==60)
miao=0;
fen=fen+1'
if(fen==60)
fen=0;
shi=shi+1'
if(shi==24)
shi=0;
elseif(key1_low)
elseif(key2_low)
fen=fen-1'
if(fen==0)
shi=shi-1'
fen=59;
=shi;
=fen;
=miao;
//显示部分
modulexianshi(clk,rst_n,en_1ms,shi,fen,miao,led_bit,dataout);
inputclk;
inputen_1ms;
input[5:
output[7:
0]led_bit;
//位选
0]dataout;
//段选
//数码管显示0~9对应段选输出
parameternum0=8'
b11000000,
num1=8'
b11111001,
num2=8'
b10100100,
num3=8'
b10110000,
num4=8'
b10011001,
num5=8'
b10010010,
num6=8'
b10000010,
num7=8'
b11111000,
num8=8'
b10000000,
num9=8'
b10010000;
reg[3:
0]shi1,shi2,fen1,fen2,miao1,miao2;
reg[7:
reg[2:
0]state;
//状态寄存器
led_bit<
=8'
state<
=3'
elseif(en_1ms)
=state+1'
shi1=shi/10;
shi2=shi%10;
fen1=fen/10;
fen2=fen%10;
miao1=miao/10;
miao2=miao%10;
if(state==3'
b000)
led_bit=8'
b11111110;
case(miao2)
0:
dataout<
=num0;
1:
=num1;
2:
=num2;
3:
=num3;
4:
=num4;
5:
=num5;
6:
=num6;
7:
=num7;
8:
=num8;
9:
=num9;
default:
dataout<
endcase
elseif(state==3'
b001)
b11111101;
case(miao1)
b010)
b11110111;
case(fen2)
b011)
b11101111;
case(fen1)
b100)
b10111111;
case(shi2)
b101)
b01111111;
case(shi1)
b110)
b11011011;
=dataout;
=led_bit;
//顶层模块
moduleShizhong(clk,rst_n,key1,key2,led_bit,dataout);
wireen_1s;
wireen_1ms;
wire[5:
wirekey1_low,key2_low;
fenpinfenpin_int(.clk(clk),
.rst_n(rst_n),
.en_1s(en_1s),
.en_1ms(en_1ms)
);
anjiananjian_int(.clk(clk),
.key1(key1),
.key2(key2),
.key1_low(key1_low),
.key2_low(key2_low)
shijianshijian_int(.clk(clk),
.key2_low(key2_low),
.shi(shi),
.fen(fen),
.miao(miao)
xianshixianshi_int(.clk(clk),
.en_1ms(en_1ms),
.miao(miao),
.led_bit(led_bit),
.dataout(dataout)
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