1VHDL程序实例整理Word文件下载.docx
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1VHDL程序实例整理Word文件下载.docx
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p2:
process(cnt2,B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1)
casecnt2is
when0=>
led_select<
="
11111111111110"
;
bcd_in<
=B1;
when1=>
11111111111101"
=B2;
when2=>
11111111111011"
=B3;
when3=>
11111111110111"
=B4;
when4=>
11111111101111"
=B5;
when5=>
11111111011111"
=B6;
when6=>
11111110111111"
=B7;
when7=>
11111101111111"
=B8;
when8=>
11111011111111"
=B9;
when9=>
11110111111111"
=B10;
when10=>
11101111111111"
=B11;
when11=>
11011111111111"
=B12;
when12=>
10111111111111"
=B13;
when13=>
01111111111111"
=B14;
endcase;
p3:
process(bcd_in)
casebcd_inis
when"
0000"
=>
x<
1111110"
0001"
0110000"
0010"
1101101"
0011"
1111001"
0100"
0110011"
0101"
1011011"
0110"
1011111"
0111"
1110000"
1000"
1111111"
1001"
1111011"
whenothers=>
0000000"
2.分频器设计程序
useieee.std_logic_arith.all;
entitydivider_1mis
port(clk:
instd_logic;
clk_1Hz:
outstd_logic;
clk_500Hz:
bufferstd_logic);
enddivider_1m;
architecturertlofdivider_1mis
signalcnt1:
integerrange0to1999;
integerrange0to499;
then
ifcnt1=cnt1'
highthen
cnt1<
else
=cnt1+1;
process(clk,cnt1)
ifcnt1>
=999then
clk_500Hz<
='
0'
process(clk_500Hz)
ifclk_500Hz'
eventandclk_500Hz='
ifcnt2=cnt2'
p4:
process(clk_500Hz,cnt2)
=249then
clk_1Hz<
endrtl;
3.8位移位寄存器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYREG8IS
PORT(LOAD,CLR,DIRE,EN,CLK:
INSTD_LOGIC;
DATA:
INSTD_LOGIC_VECTOR(7DOWNTO0);
DOUT:
BUFFERSTD_LOGIC_VECTOR(7DOWNTO0));
ENDREG8;
ARCHITECTUREAOFREG8IS
BEGIN
PROCESS(LOAD,CLR,DIRE,EN,CLK)
VARIABLEX:
STD_LOGIC;
BEGIN
IFLOAD='
THENDOUT<
=DATA;
ELSIFCLR='
00000000"
ELSIFEN='
=DOUT;
ELSIFCLK'
EVENTANDCLK='
THEN
IFDIRE='
THEN
X:
=DOUT(7);
DOUT(7DOWNTO1)<
=DOUT(6DOWNTO0);
DOUT(0)<
=X;
ELSE
=DOUT(0);
DOUT(6DOWNTO0)<
=DOUT(7DOWNTO1);
DOUT(7)<
ENDIF;
ENDIF;
ENDPROCESS;
ENDA;
4.BCD计数器设计(任意进制)
LIBRARYieee;
useieee.std_logic_unsigned.all;
ENTITYcnt365IS
PORT(clk,reset:
daout:
outstd_logic_vector(9downto0));
END;
ARCHITECTUREfunOFcnt365IS
SIGNALcount:
STD_LOGIC_VECTOR(9downto0);
daout<
=count;
p1:
process(clk,reset)
begin
if(reset='
)then
count<
="
0000000000"
elsif(clk'
ifcount(9downto0)="
1101100100"
then
count(9downto0)<
elsifcount(7downto0)="
10011001"
count<
=count+"
01100111"
elsifcount(3downto0)="
=count+1;
endprocessp1;
ENDfun;
5.基于状态机的计数器设计
entitystatemachine_counteris
port(clr,clk:
q:
outstd_logic_vector(2downto0));
architectureaofstatemachine_counteris
typestate_typeis(s0,s1,s2,s3,s4,s5,s6);
signalpresent_state,next_state:
state_type;
process(clk,clr)
ifclr='
then
present_state<
=s0;
elsifclk'
=next_state;
endprocessp1;
process(clk,present_state)
casepresent_stateis
whens0=>
next_state<
=s1;
whens1=>
=s2;
whens2=>
=s3;
whens3=>
=s4;
whens4=>
=s5;
whens5=>
=s6;
whens6=>
endprocessp2;
p3:
process(clr,present_state)
q<
000"
q<
001"
010"
011"
100"
101"
110"
endprocessp3;
enda;
6.LED灯控制
--设计一个循环彩灯控制器
--该控制器控制红,绿,黄三个发光二极管循环发亮
--要求红发光管亮2秒,绿亮3秒,黄亮1秒。
ENTITYASM_LEDIS
PORT(CLR:
INSTD_LOGIC;
--清零控制输入
CLK:
--时钟输入
LED1:
OUTSTD_LOGIC;
--LED1输出
LED2:
--LED2输出
LED3:
OUTSTD_LOGIC);
--LED3输出
ENDASM_LED;
--实体名称可以省略
---------------------------------------------
ARCHITECTUREAOFASM_LEDIS
TYPESTATE_TYPEIS(S0,S1,S2,S3,S4,S5,S6);
--枚举类型,状态
SIGNALPRESENT_STATE,NEXT_STATE:
STATE_TYPE;
--定义信号
BEGIN
----------------------------------
P1:
PROCESS(CLK,CLR)--进程1,判断时钟端与清零端,从而得到当前状态
BEGIN--开始
IFCLR='
THEN--如果清零端有效
PRESENT_STATE<
=S0;
--当前状态就为S0
ELSIFCLK'
THEN--如果有上升沿到来
=NEXT_STATE;
--当前状态就变为下一个状态
ENDIF;
ENDPROCESSP1;
---------------------------------------
P2:
PROCESS(CLK,PRESENT_STATE)--进程2,
CASEPRESENT_STATEIS
WHENS0=>
NEXT_STATE<
=S1;
WHENS1=>
=S2;
WHENS2=>
=S3;
WHENS3=>
=S4;
WHENS4=>
=S5;
WHENS5=>
=S6;
WHENS6=>
ENDCASE;
ENDPROCESSP2;
--------------------------------------
P3:
PROCESS(CLR,PRESENT_STATE)--进程3
LED1<
LED2<
LED3<
ELSE
CASEPRESENT_STATEIS
WHENS0=>
LED1<
WHENS1=>
--LED1(黄色发光管点亮1秒)
WHENS2=>
--LED2(红色发光管点亮2秒)
WHENS3=>
WHENS4=>
--LED3(绿色发光管点亮3秒)
WHENS5=>
WHENS6=>
ENDCASE;
ENDPROCESSP3;
7.BCD显示译码器
entitydecoder7is
port(bcd:
instd_logic_vector(3downto0);
dout:
outstd_logic_vector(6downto0));
enddecoder7;
architecturertlofdecoder7is
process(bcd)
casebcdis
whenb"
dout<
=b"
0111111"
0000110"
1001111"
1100110"
1111101"
0000111"
1101111"
null;
endprocess;
endrtl;
8.100M频率计设计
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYFREQUENCY_TESTIS
PORT(FSIN:
CLK:
DOUT:
OUTSTD_LOGIC_VECTOR(31DOWNTO0));
ENDFREQUENCY_TEST;
ARCHITECTUREBEHAVEOFFREQUENCY_TESTIS
SIGNALTEST_EN:
SIGNALCLEAR:
SIGNALDATA:
STD_LOGIC_VECTOR(31DOWNTO0);
PROCESS(CLK)
IFCLK'
THEN
TEST_EN<
=NOTTEST_EN;
CLEAR<
=NOTCLKANDNOTTEST_EN;
PROCESS(FSIN)
IFCLEAR='
DATA<
00000000000000000000000000000000"
ELSIFFSIN'
EVENTANDFSIN='
IFDATA(31DOWNTO0)="
10011001100110011001100110011001"
=DATA+"
01100110011001100110011001100111"
ELSIFDATA(27DOWNTO0)="
1001100110011001100110011001"
0110011001100110011001100111"
ELSIFDATA(23DOWNTO0)="
100110011001100110011001"
011001100110011001100111"
ELSIFDATA(19DOWNTO0)="
10011001100110011001"
01100110011001100111"
ELSIFDATA(15DOWNTO0)="
1001100110011001"
0110011001100111"
ELSIFDATA(11DOWNTO0)="
100110011001"
011001100111"
ELSIFDATA(7DOWNTO0)="
ELSIFDATA(3DOWNTO0)="
ELSE
=DATA+'
PROCESS(TEST_EN,DATA)
IFTEST_EN'
EVENTANDTEST_EN='
DOUT<
ENDBEHAVE;
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