华北电力大学科技学院EDA试验代码Word下载.docx
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华北电力大学科技学院EDA试验代码Word下载.docx
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BEGIN
PROCESS(clk)IS
IFclk'
EVENTANDclk='
1'
THEN
q<
=d;
ENDIF;
ENDPROCESS;
ENDARCHITECTURErt1;
2
ENTITYshift_reg8IS
GENERIC(N:
INTEGER:
=8);
PORT(a,clk:
INSTD_LOGIC;
ENDENTITYshift_reg8;
ARCHITECTURErt1OFshift_reg8IS
COMPONENTd_ffIS
ENDCOMPONENTd_ff;
SIGNALs:
STD_LOGIC_VECTOR(1to(N-1));
BEGIN
g1:
FORIin0TO(N-1)GENERATE
g2:
IFi=0GENERATE
dffx:
d_ffPORTMAP(a,clk,s(i+1));
ENDGENERATE;
g3:
IFi=(N-1)GENERATE
d_ffPORTMAP(s(i),clk,b);
g4:
IF((i/=0)AND(i/=N-1))GENERATE
d_ffPORTMAP(s(i),clk,s(i+1));
实验三:
过程的输出参数做信号使用
1:
PACKAGEmy_vhdl_pacIS
PROCEDUREmax(a,b:
INstd_logic_vector(7downto0);
signaly:
OUTstd_logic_vector(7downto0));
ENDPACKAGEmy_vhdl_pac;
PACKAGEBODYmy_pacIS
OUTstd_logic_vector(7downto0)IS
IF(a<
b)THEN
y<
=b;
ELSE
y<
=a;
ENDIF;
ENDPROCEDUREmax;
ENDPACKAGEBODYmy_vhdl_pac;
USEWORKmy_vhdl_pac.ALL;
ENTITYcompIS
PORT(d1:
INSTD_LOGIC_VECTOR(7DWONTO0);
d2:
INSTD_LOGIC_VECTOR(7DWONTO0);
rt:
:
OUTSTD_LOGIC_VECTOR(7DWONTO0));
ENDENTITYcomp;
ARCHITECTURErtlOFcompIS
BEGIN
max(d1,d2,rt);
过程做变量
OUTstd_logic_vector(7downto0))IS
y:
y:
PROCESS(d1,d2)IS
VARIABLEtmp:
STD_LOGIC_VECTOR(7DWONTO0);
max(d1,d2,tmp);
rt<
=tmp;
ENDPROCESS;
2:
ENTITYtype_convIS
ININTEGERRANGE0TO9;
INSTD_LOGIC_VECTOR(3DOWNTO0);
c:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
d:
OUTINTEGERRANGE0TO9);
ENDENTITYtype_conv;
ARCHITECTURErtlOFtype_convIS
=CONV_STD_LOGIC_VECTOR(a,4);
d<
=CONV_INTEGER(b);
实验四(都是同步复位)
1信号做计数器
ENTITYcnt6IS
PORT(clk:
dout:
OUTINTEGERRANGE0TO5);
ENDENTITYcnt6;
ARCHITECTURErtlOFcnt6IS
SIGNALtmp:
INTEGERRANGE0TO5:
=0;
PROCESS(clk)IS
IFtmp=5THEN
tmp<
=tmp+1;
dout<
2变量作计数器
VARIABLEtmp:
tmp:
ENDARCHITECTURErtl;
实验五
ENTITYfull_adderIS
PORT(a,b,c:
s,co:
ENDENTITYfull_adder;
ARCHITECTURErtlOFfull_adderIS
SIGNALa_n,b_n,c_n:
STD_LOGIC;
SIGNALm1,m2,m3,m4,m5,m6,m7:
a_n<
=NOTa;
b_n<
=NOTb;
c_n<
=NOTc;
m1<
=a_nANDb_nANDc;
m2<
=a_nANDbANDc_n;
m3<
=a_nANDbANDc;
m4<
=aANDb_nANDc_n;
m5<
=aANDb_nANDc;
m6<
=aANDbANDc_n;
m7<
=aANDbANDc;
=m1ORm2ORm4ORm7;
co<
=m3ORm5ORm6ORm7;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYaluIS
PORT(a,b:
c,d:
OUTSTD_LOGIC_VECTOR(4DOWNTO0);
e:
OUTSTD_LOGIC_VECTOR(7DOWNTO0);
f:
OUTSTD_LOGIC_VECTOR(4DOWNTO0));
ENDENTITYalu;
ARCHITECTURErtlOFaluIS
SIGNALt1,t2,t3:
INTEGER;
t1<
=CONV_INTEGER(a);
t2<
c<
='
0'
&
a+b;
d<
a-b;
e<
=a*b;
t3<
=t1/t2;
f<
=CONV_STD_LOGIC_VECTOR(t3,5);
实验六
1八选一数据选择器CASE
ENTITYmun_8_1IS
PORT(e_n,d0,d1,d2,d3,d4,d5,d6,d7,s2,s1,s0:
y,y_n:
ENDENTITYmun_8_1;
ARCHITECTURErtlOFmun_8_1IS
SIGNALsel:
STD_LOGIC_VECTOR(2DOWNTO0);
SIGNALtmp:
sel<
=s2&
s1&
s0;
PROCESS(d0,d1,d2,d3,d4,d5,d6,d7,sel)IS
CASE(sel)IS
WHEN"
000"
=>
tmp<
=d0;
001"
=d1;
010"
=d2;
011"
=>
=d3;
100"
=d4;
101"
=d5;
110"
=d6;
111"
=d7;
WHENOTHERS=>
X'
;
ENDCASE;
PROCESS(tmp,e_n)IS
IFe_n='
y_n<
=NOTtmp;
ELSE
八位八选一数据选择器CASE
ENTITYmux_8_1IS
PORT(d0,d1,d2,d3,d4,d5,d6,d7:
INSTD_LOGIC_VECTOR(7DOWNTO0);
e_n,s2,s1,s0:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDENTITYmux_8_1;
ARCHITECTURErtlOFmux_8_1IS
STD_LOGIC_VECTOR(7DOWNTO0);
="
XXXXXXXX"
00000000"
11111111"
2八选一数据选择器IF
ENTITYmux8IS
ENDENTITYmux8;
ARCHITECTURErtlOFmux8IS
IF(sel="
)THEN
ELSIF(sel="
y_n<
八位八选一数据选择器IF
e_n,s2,s1,s0:
=(others=>
'
);
实验七
1八选一数据选择器条件
sel<
=d0WHENsel="
d1WHENsel="
d2WHENsel="
d3WHENsel="
d4WHENsel="
d5WHENsel="
d6WHENsel="
d7WHENsel="
'
1.八位八选一数据选择器条件信号赋值
s2,s1,s0:
"
2八选一数据选择器选择信号赋值
WITHselSELECT
=d0WHEN"
d1WHEN"
d2WHEN"
d3WHEN"
d4WHEN"
d5WHEN"
d6WHEN"
d7WHEN"
WHENOTHERS;
2八位
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