DSP外部电路设计的经典著作图文精Word文件下载.docx
- 文档编号:21643261
- 上传时间:2023-01-31
- 格式:DOCX
- 页数:48
- 大小:794.95KB
DSP外部电路设计的经典著作图文精Word文件下载.docx
《DSP外部电路设计的经典著作图文精Word文件下载.docx》由会员分享,可在线阅读,更多相关《DSP外部电路设计的经典著作图文精Word文件下载.docx(48页珍藏版)》请在冰豆网上搜索。
Interfacingwiththereal
world000000004.900
00
004.10Questions4.11References
208Chapter4❚DSPsystems–interfacingwiththeoutsideworld
DSPdevices–beyondthecore
209
Memorystructures
TheideaoftheHarvardarchitectureusedwithinmostDSPdeviceshasalreadybeenintroducedinChapter3.Harvardarchitectures,asalreadymentioned,makeuseofsepa-rateprogramanddatastorageareasthatcanbesimultaneouslyaccessed.ThismakesmanyprocessingoperationsfarmoreefficientthanwouldbepossibleonatraditionalVonNeumannarchitecture.Theprogramanddatastorageareasmaybeconstructedusingarangeofdifferentmemorytypesasappropriateforanygivenapplication.MostDSPsareprovidedwithalimitedamountofon-chipmemorywhichcanbeaccessedatfullspeed;
alsothisisusuallydividedintoprogramanddataareaswhichcantrulybeaccessedsimul-taneously.Ifextramemoryspaceisrequiredforaparticularapplication,thenthiscanbeaddedviaanexternalmemoryinterfacewhichprovidesdata,addressandcontrolbusestotheoutsideworld.Oneoftheproblemswithinterfacestoexternalmemoryisthattheon-chipdualbusarchitectureisrarelyreplicatedtotheoutsideworldandsosimultaneousaccesstoexternalmemoryarenotpossible.Forthisreason,high-speedprocessingopera-tions,usingsimultaneousaccessestomemory,usuallyrequiresthatdataandprograminstructionsresideon-chip(Ref.4.1.
ItiscommonpracticetorepresenttheaddressablememoryorI/OspaceofaDSPdeviceusingamemorymap.ThememorymapofaTMS320C54xDSPdeviceisshowninFigure4.2.Infact,thisisthememorymapofaC548DSPdevicewhichisoneofanumberofdifferentdeviceswithintheC54xfamily.ThememorymapofFigure4.2,whichisquitetypicalofmanyDSPdevices,showsthetwoidentifiableareasofprogramanddatamemory.Thisisfurthersubdividedintoareasofinternalandexternalmemoryspace.Thememoryspacedefinedforthisdeviceisactuallyorganizedintothreeindividu-allyselectablespaceslabelledasprogram,data,andI/Ospace.
ThememorymapoftheC548DSPshowninFigure4.2canbesettooneofanumberofdifferentconfigurationsaccordingtosettingsgivenintheProcessorModeStatusRegister,PMST,associatedwiththisdevice.TheoperationofthePMSTregisterisdis-cussedinSection3.7.5.Insummary,tworegisterflagsareimportantformemoryconfigurationontheC54xdevices,theOVLYflagandtheMP/MCflag.TheOVLYflagisusedtoenableordisablethemappingofdatamemoryintoprogrammemoryspaceandtheMP/MCflagisusedtoenableordisabletheon-chipROMandhencedeterminesthebootmodeofthedevice.
MostDSPdevicesareprovidedwithalimitedamountofon-chipread-onlymemory,ROM,andrandomaccessmemory,RAM,andtheC54xisnoexceptiontothis.AllC54xdevicescontainbothRAMandROM.AmongthedifferentC54xdevices,twotypesofRAMarerepresented:
dual-accessRAM,DARAM,andsingle-accessRAM,SARAM.Table4.1showstheallocationofinternalmemoryforeachofthedifferentdevicesintheC54xfamily.On-chipROM.Theon-chipROMispartoftheprogrammemoryspaceand,forsomedevices,formspartofthedatamemoryspace.Theamountofon-chipROMavailableoneachdevicevaries,asindicatedinTable4.1.OndeviceswithasmallamountofROM(2Kwords,theROMcontainsabootloader,whichisusefulforbootingtofasteron-chiporexternalRAMduringthestart-upsequence.ThebootloaderalgorithminitializestheDSPtoaknownstateandprovidesasimplemechanismbywhichtheuser’sapplicationcodecanbeloadedontotheDSPandprogramexecutioninitiated.Thebootloaderisveryflex-4.1.1
210Chapter4❚DSPsystems–interfacingwiththeoutsideworld
Figure4.2Memory
mapshowingthe
programanddata
spacedefinedfora
TMS320C548DSP
device
Table4.1Texas
InstrumentsC54x
DSP–on-chip
memory
DSPdevices–beyondthecore211
ibleandallowstheapplicationcodetobeloadedfromslowexternalROMsorviaaserialinterface,hostportorthroughtheuseofJTAG.OndeviceswithlargeramountsofROM,aportionoftheROMmaybemappedintobothdataandprogramspace.ThelargerROMsarealsocustomROMs:
wheretheuserprovidesthecodeordatatobepro-grammedintotheROMinobjectfileformatandTexasInstrumentsgeneratestheappropriateprocessmasktoprogramtheROM.
On-chipdual-accessRAM(DARAM.TheDARAMiscomposedofseveralblocks.BecauseeachDARAMblockcanbeaccessedtwicepermachinecycle,thecentralprocess-ingunit,CPU,canreadfromandwritetoasingleblockofDARAMinthesamecycle.TheDARAMisalwaysmappedindataspaceandisprimarilyintendedtostoredatavalues.Itcanalsobemappedintoprogramspaceandusedtostoreprogramcode.
On-chipsingle-accessRAM(SARAM.TheSARAMisalsocomposedofseveralblocks.Eachblockisaccessibleoncepermachinecycleforeitherreadingorwriting.TheSARAMisalwaysmappedindataspaceandisprimarilyintendedforstorageofdatavalues.Itcanalsobemappedintoprogramspaceandusedtostoreprogramcode.
Memory-mappedregisters.Thedatamemoryspacecontainsmemory-mappedregistersfortheCPUandtheon-chipperipherals.Theseregistersarelocatedondatapage0,sim-plifyingaccesstothem.Thememory-mappedaccessprovidesaconvenientwaytosaveandrestoretheregistersforcontextswitchesandtotransferinformationbetweentheaccumulatorsandtheotherregisters.
IthasbeenmentionedthattheC54xDSPpresentedinthisexampleisabletomakeuseofdual-accessRAM,DARAM.ThistypeoffastrandomaccessmemorycanbewrittentoorreadfromtwiceineachinstructioncycleandhencethepotentialdatathroughputrateoftheDSPdeviceisincreased.Dualaccessesareachievedthroughtheuseofamultiplebusarchitecture,asshowninFigure4.3.ThediagramofFigure4.3showstheeightinternalbusesusedontheC54xDSP.Ofthese,fourareallocatedtoaddressingandanotherfourallocatedtocarryprogramordatainformation.Specifically,theC54xDSPusesthreeinternaldata‘highways’labelledCB,DBandEBwithassociatedaddressbusesCAB,CDBandCEBrespectively.AlsooneofthebussesisallocatedtocarryingprograminstructionsandislabelledPBwithanassociatedprogramaddressbus,PAB.
AlthoughinternallymanyDSPdevices,includingtheC54x,arestructuredwithamultibusarchitecture,thisisrarelyreplicatedtotheoutsideworld.MostDSPsarepro-videdwithsomesortofmemoryinterfacethatwillmultiplextheinternalmultibusstructuredowntoasinglesetofexternalI/Olinesincludingonefull-widthaddressanddatabus.InthecaseoftheC54xDSPthisinterfaceisrepresentedbytheblockshownontherighthandsideofFigure4.3.Thisfactisconfirmedbyobservingexternalpinconnec-tionsprovidedontheDSPchipitself,asidentifiedinFigure4.4.
Addressgenerationunits
BecauseDSPdevicesmakeuseofaHarvardarchitectureincorporatingatleastoneprogramanddatamemoryarea,theywillusuallyhaveseparatehardwaretogeneratetherequiredaddressinginformation.Inthecaseoftheprogramaddressgenerationunit,thiswillincor-poratetheprograminstructioncounter,PC,whichisusedtostepthroughtheprogram4.1.2
212Chapter4❚DSPsystems–interfacingwiththeoutsideworld
Figure4.3Texas
InstrumentsC54xDSP
deviceinternal
addressand
data/programbus
architecture
Figure4.4Texas
externalinterface
connections
213
instructions.Theprogramaddressgeneratorisusuallycapableofsimplearithmeticopera-tionssothatitcancalculateandperformbranchesforwardandbackwardintoprogrammemoryspace.Theprogramaddressgenerationunitisalsooftenabletoperformhardwareloopingofinstructionssothatasegmentofcodecanberunanumberoftimeswithverylittleadditionalprocessingoverhead.Inordertoperformhardwareloopingtheprogramaddressgeneratorusuallyincorporatesaloopcounter,whichdecrementseverytimetheseg-mentofcodehasrun,andaloopstartandstopaddressregister,sothatthebeginningandendofthecodesegmentcanbeidentified.Finally,theprogramaddressgenerationunitusu-allyperformsprogramjumpstointerruptvectoraddresses.WhenaDSPinterruptlineisenabled,thecurrentvalueoftheprogramcounter,PC,isstoredontothesystemstackandtheappropriateaddressoftheinterruptserviceroutineistemporarilyplacedintothePC.Whentheinterruptserviceroutinehascompleteditsoperation,programexecutionisreturnedtowhereitleftoffbyrestoringtheoriginalPCvaluefromthestack.
Thedataaddressgenerationunitisusuallyabletoperformanumberofarithm
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- DSP 外部 电路设计 经典著作 图文