复杂数字电路设计实验报告数字抢答器Word下载.docx
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复杂数字电路设计实验报告数字抢答器Word下载.docx
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|IOSTANDARD=lvcmos33;
加分:
up"
L14"
|IOSTANDARD=lvttl|PULLUP;
扣分:
down"
L13"
A组抢答按钮:
K1"
H13"
|IOSTANDARD=lvttl|PULLDOWN;
B组抢答按钮:
K2"
V4"
C组抢答按钮:
K3"
D18"
D组抢答按钮:
K4"
K17"
LED提示灯:
outalarm"
F9"
|IOSTANDARD=lvttl|SLEW=slow|DRIVE=8;
抢答重置:
reset"
N17"
得分重置:
resetl"
H18"
LCD各使能端与数据线:
LCD_RS"
L18"
|IOSTANDARD=LVCMOS33|DRIVE=4|SLEW=SLOW;
LCD_RW"
L17"
LCD_EN"
M18"
data<
3>
"
M15"
2>
P17"
1>
R16"
0>
R15"
四.实验代码设计以及分析:
1.给出模块层次图;
2.按模块完成的代码及注释.
Justify模块(第一信号鉴别及锁存模块):
entityjustifyis
Port(K1:
inSTD_LOGIC;
K2:
K3:
K4:
reset:
--不弹起的开关
clr:
output:
bufferSTD_LOGIC_VECTOR(3downto0):
="
0000"
;
outalarm:
outSTD_LOGIC:
='
0'
);
endjustify;
architectureBehavioralofjustifyis
signalK11,K22,K33,K44:
STD_LOGIC:
signalalarm:
signaltempoutput:
STD_LOGIC_VECTOR(3downto0):
begin
alarm<
=output(0)oroutput
(1)oroutput
(2)oroutput(3);
--有人抢到题,该答了
K11<
=K1ANDNOT(output
(1)ORoutput
(2)ORoutput(3));
--禁止别人再抢答
K22<
=K2ANDNOT(output(0)ORoutput
(2)ORoutput(3));
K33<
=K3ANDNOT(output(0)ORoutput
(1)ORoutput(3));
K44<
=K4ANDNOT(output(0)ORoutput
(1)ORoutput
(2));
FindFirst:
PROCESS(clr,reset,K11,K22,K33,K44)IS
if(reset='
orclr='
)then—清零
tempoutput(3downto0)<
elsif(K11='
1'
)then
0001"
elsif(K22='
0010"
elsif(K33='
0100"
elsif(K44='
1000"
endif;
endPROCESSFindFirst;
KeepValue:
PROCESS(alarm,tempoutput,reset,clr)IS—锁存
output(3downto0)<
elsif(alarm='
=tempoutput(3downto0);
endPROCESSKeepValue;
outalarm<
=alarm;
endBehavioral;
Violation模块(抢答鉴别及锁存模块):
entityviolationjustifyis
Port(clk500:
K1:
clr:
reset:
violation:
);
endviolationjustify;
architectureBehavioralofviolationjustifyis
signaltempoutput:
signalclk:
STD_LOGIC;
clk<
=clk500andnot(reset);
violation<
--alarm+flag
FindViolation:
PROCESS(clr,clk,reset)IS
begin
if(clr='
tempoutput<
elsif(clk'
eventandclk='
)then—有人犯规
if(K1='
tempoutput(0)<
endif;
if(K2='
tempoutput
(1)<
if(K3='
tempoutput
(2)<
if(K4='
tempoutput(3)<
endif;
endprocessFindViolation;
output<
=tempoutput;
分频器:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entitydivideris
Port(clk_50M:
clk_1:
outSTD_LOGIC;
clk_500:
outSTD_LOGIC);
enddivider;
architectureBehavioralofdivideris
signalCCLK_500,CCLK_1:
STD_LOGIC:
='
process(clk_50M)
variablecount1:
integerrange1to25000000:
=1;
--1hz
variablecount3:
integerrange1to50000:
--500Hz
if(clk_50M'
EVENTandclk_50M='
if(count1=25000000)then--25000000,10
count1:
--1Hz
CCLK_1<
=NOT(CCLK_1);
else
=count1+1;
endif;
if(count3=50000)then--50000
count3:
CCLK_500<
=NOT(CCLK_500);
=count3+1;
endprocess;
clk_500<
=CCLK_500;
--500hz
clk_1<
=CCLK_1;
记分模块:
entitypointsis
Port(
input:
inSTD_LOGIC_VECTOR(3downto0);
add:
minus:
resetforpoints:
point_ten_A,point_ten_B,point_ten_C,point_ten_D:
outSTD_LOGIC_VECTOR(3downto0):
point_one_A,point_one_B,point_one_C,point_one_D:
endpoints;
architectureBehavioralofpointsis
signalkey:
key<
=addorminus;
--按下加分或减分
process(key,resetforpoints)is
variableppoint_ten_A,ppoint_ten_B,ppoint_ten_C,ppoint_ten_D:
STD_LOGIC_VECTOR(3downto0):
variableppoint_one_A,ppoint_one_B,ppoint_one_C,ppoint_one_D:
if(resetforpoints='
)then—分数重置
ppoint_one_A:
ppoint_ten_A:
ppoint_one_B:
ppoint_ten_B:
ppoint_one_C:
ppoint_ten_C:
ppoint_one_D:
ppoint_ten_D:
else
if(key'
eventandkey='
)then—加分
if(add='
if(input="
if(ppoint_one_A="
1001"
ppoint_one_A:
ppoint_ten_A:
=ppoint_ten_A+1;
else
=ppoint_one_A+1;
endif;
elsif(input="
if(ppoint_one_B="
ppoint_one_B:
ppoint_ten_B:
=ppoint_ten_B+1;
=ppoint_one_B+1;
if(ppoint_one_C="
ppoint_one_C:
ppoint_ten_C:
=ppoint_ten_C+1;
=ppoint_one_C+1;
if(ppoint_one_D="
ppoint_one_D:
ppoint_ten_D:
=ppoint_ten_D+1;
=ppoint_one_D+1;
--input
elsif(minus='
)then—减分
if(input(0)='
=ppoint_ten_A-1;
=ppoint_one_A-1;
if(input
(1)='
=ppoint_ten_B-1;
=ppoint_one_B-1;
if(input
(2)='
=ppoint_ten_C-1;
=ppoint_one_C-1;
if(input(3)='
=ppoint_ten_D-1;
=ppoint_one_D-1;
point_one_A<
=ppoint_one_A;
point_ten_A<
=ppoint_ten_A;
point_one_B<
=ppoint_one_B;
point_ten_B<
=ppoint_ten_B;
point_one_C<
=ppoint_one_C;
point_ten_C<
=ppoint_ten_C;
point_one_D<
=ppoint_one_D;
point_ten_D<
=ppoint_ten_D;
防抖模块:
entityshakingis
input:
endshaking;
architectureBehavioralofshakingis
signalflag:
process(clk500,input)is
variablecount:
integer:
=0;
if(clk500'
eventandclk500='
if(input='
andcount=0)then—有输入,将输入延展
count:
=count+1;
flag<
elsif(flag='
if(count<
500)then--500
count:
else
flag<
=flag;
用于判断是否答题超时的计时模块(Timer)
entitytimeris
Port(clk1:
--1hz
violationflag:
clr:
resetforpoints:
timeout:
endtimer;
architectureBehavioraloftimeris
signalen:
en<
=resetandclrandresetforp
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