并行乘法器南京理工大学紫金学院vhdl实验报告edaWord文件下载.docx
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并行乘法器南京理工大学紫金学院vhdl实验报告edaWord文件下载.docx
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并行乘法器的电路原理图如下图所示,主要由全加器和与门构成。
證⑵
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*丄%
-n
p⑷
并行乘法器原理图
实验内容
1、and_2
libraryieee;
useieee.std_logic_1164.all;
entityand_2is
port(a,b:
instd_logic;
y:
outstd_logic);
endand_2;
architectureand_2ofand_2is
begin
y<
=aandb;
2、faulibraryieee;
entityfauis
port(a,b,cin:
s,cout:
endfau;
architecturefauoffauisbegin
s<
=axorbxorcin;
cout<
=(aandb)or(aandcin)or(bandcin);
3、top_rowlibraryieee;
usework.my_components.all;
entitytop_rowis
port(a:
b:
instd_logic_vector(3downto0);
sout,cout:
outstd_logic_vector(2downto0);
p:
endtop_row;
architecturestructuraloftop_rowisbegin
U1:
componentand_2portmap(a,b(3),sout
(2));
U2:
componentand_2portmap(a,b
(2),sout
(1));
U3:
componentand_2portmap(a,b
(1),sout(0));
U4:
componentand_2portmap(a,b(0),p);
cout
(2)<
='
0'
;
cout
(1)<
cout(0)<
4、mid_rowlibraryieee;
entitymid_rowis
sin,cin:
instd_logic_vector(2downto0);
endmid_row;
architecturestructuralofmid_rowis
signaland_out:
std_logic_vector(2downto0);
componentand_2portmap(a,b
(2),and_out
(2));
componentand_2portmap(a,b
(1),and_out
(1));
componentand_2portmap(a,b(0),and_out(0));
U5:
componentfauportmap(sin
(2),cin
(2),and_out
(2),
sout
(1),cout
(2));
U6:
componentfauportmap(sin
(1),cin
(1),and_out
(1),
sout(0),cout
(1));
U7:
componentfauportmap(sin(0),cin(0),and_out(0),
p,cout(0));
endstructural;
5、lower_rowlibraryieee;
entitylower_rowis
port(sin,cin:
outstd_logic_vector(3downto0));
architecturestructuraloflower_rowis
signallocal:
local(0)<
componentfauportmap(sin(0),cin(0),local(0),
p(0),local
(1));
componentfauportmap(sin
(1),cin
(1),local
(1),
p
(1),local
(2));
componentfauportmap(sin
(2),cin
(2),local
(2),
p
(2),p(3));
6、my_componentslibraryieee;
packagemy_componentsiscomponentand_2is
y:
endcomponent;
componentfauis
s,cout:
componenttop_rowis
componentmid_rowis
componentlower_rowis
endmy_components;
7、multiplierlibraryieee;
entitymultiplieris
prod:
outstd_logic_vector(7downto0));
endmultiplier;
architecturestructuralofmultiplieris
typematrixisarray(0to3)of
std_logic_vector(2downto0);
signals,c:
matrix;
componenttop_rowportmap(a(0),b,s(0),c(0),
prod(0));
componentmid_rowportmap(a
(1),b,s(0),c(0),s
(1),
c
(1),prod
(1));
componentmid_rowportmap(a
(2),b,s
(1),c
(1),s
(2),
c
(2),prod
(2));
componentmid_rowportmap(a(3),b,s
(2),c
(2),s(3),
c(3),prod(3));
componentlower_rowportmap(s(3),c(3),
prod(7downto4));
8、仿真
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9、把
multiplier代码改为百位、十位、个位输出代码如下:
MaieiTneEyMit
useieee.std_logic_unsigned.all;
usework.my_components.all;
entitymultiplieris
instd_logic_vector(3downto0);
hun,ten,one:
outstd_logic_vector(3downto0));
endmultiplier;
architecturestructuralofmultiplieris
std_logic_vector(2downto0);
signals,c:
signalp:
std_logic_vector(7downto0);
p(0));
c
(1),p
(1));
c
(2),p
(2));
c(3),p(3));
componentlower_rowportmap(s(3),c(3),
p(7downto4));
process(p)variabletemp:
ifp>
"
1100_0111"
then
hun<
="
0010"
temp:
=p-"
1100_1000"
elsifp>
0110_0011"
0001"
0110_0100"
else
0000"
=p;
endif;
iftemp>
0101_1001"
ten<
1001"
=temp-"
0101_1010"
elsiftemp>
0100_1111"
1000"
1010_0000"
0100_0101"
0111"
0100_0110"
0011_1011"
0110"
0011_1100"
0011_0001"
0101"
0011_0010"
0010_0111"
0100"
0010_1000"
0001_1101"
0011"
0001_1110"
0001_0011"
0001_0100"
0000_1001"
0000_1010"
=temp;
one<
=temp(3downto0);
endprocess;
四、小结与体会
通过本次实验,我对包集和元件例化语句的使用有了更深刻的了解。
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