计算机组成原理实验5文档格式.docx
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计算机组成原理实验5文档格式.docx
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h11:
h0180020014;
h12:
h0000000401;
h13:
h8000000401;
h14:
h0010002001;
h15:
h5010020816;
h16:
h440a7a0017;
h17:
h44099a0018;
h18:
h440eca0019;
h19:
h440f8a0000;
h1a:
h401003401b;
h1b:
h401003501c;
h1c:
h401003501d;
h1d:
h401002a01f;
h1e:
h0000000000;
h1f:
h4020025030;
h20:
h21:
h000a780c01;
h22:
h0009980c01;
h23:
h000ec80c01;
h24:
h0008180c01;
h25:
h000e80800e;
h26:
h000fc08010;
h27:
h0000000112;
h28:
h0000000212;
h29:
h000fc02401;
h2a:
h000e800401;
h2b:
h0040002401;
h2c:
h0100000001;
h2d:
h0200000001;
h2e:
h0000020401;
h2f:
h30:
h4020025031;
h31:
h4020020000;
h32:
h5010020833;
h33:
h64100c0834;
h34:
h7810020835;
h35:
h4c1002a036;
h36:
h400e834037;
h37:
h440e835038;
h38:
h480e835039;
h39:
h4c0e83503a;
h3a:
h4c1002803b;
h3b:
h702002483c;
h3c:
h6c2002483d;
h3d:
h582002483e;
h3e:
h4420024800;
h3f:
default:
beginend
endcase
end
endmodule
rom64_40.vt
`timescale1ns/1ps
modulerom64_40_vlg_tst();
reg[5:
wire[39:
rom64_40i1(
.addr(addr),
.q(q)
);
integeri;
initial
begin
for(i=0;
i<
64;
i=i+1)
#50addr=i;
end
end
endmodule
rom64_40.bsf
rom64_40.bsf仿真测试
Reg6.v
modulereg6(CLK,DOUT,D,CLR_);
inputCLK;
wireCLK;
0]D;
wire[5:
inputCLR_;
wireCLR_;
output[5:
0]DOUT;
reg[5:
always@(negedgeCLKornegedgeCLR_)
if(CLR_==0)
DOUT<
=6'
d0;
else
=D;
reg6.vt
`timescale1ps/1ps
modulereg6_vlg_tst();
regCLK;
regCLR_;
0]D;
wire[5:
0]DOUT;
reg6i1(
.CLK(CLK),
.CLR_(CLR_),
.D(D),
.DOUT(DOUT)
initial
begin
CLK=0;
D=6'
d1;
CLR_=1;
#10CLR_=0;
#10CLR_=1;
#30D=6'
d2;
always
#20CLK=~CLK;
#50
for(i=3;
15;
#40D=i;
reg6.bsf
reg6功能仿真
Addrtran.bdf
addrtran.vt
moduleaddrtran_vlg_tst();
regeachvec;
regC;
regINT;
reg[7:
4]IR;
0]NuA;
reg[4:
0]P;
regSWA;
regSWB;
regSWC;
regZ;
0]uA;
addrtrani1(
.C(C),
.\INT(INT),
.IR(IR),
.NuA(NuA),
.P(P),
.SWA(SWA),
.SWB(SWB),
.SWC(SWC),
.uA(uA),
.Z(Z)
INT=0;
C=0;
Z=0;
P=5'
NuA=2'
o01;
SWC=0;
SWB=0;
SWA=0;
#20SWA=1;
#20SWA=0;
SWB=1;
SWB=0;
SWC=1;
#20SWC=0;
P=5'
NuA=6'
d010000;
#80
16;
#20IR=i;
addrtran.bsf
Addrtran功能仿真
Micro_controller.bdf
Micro_controller.v
modulemicro_controller(
SWC,
SWB,
SWA,
C,
Z,
INT,
T3,
CLR_,
IR,
PCADD,
SELCTL,
INTEN,
INTDI,
LIAR,
IABUS,
MBUS,
SBUS,
ABUS,
M,
CIN,
LDC,
LDZ,
LIR,
STOP,
MEMW,
LAR,
ARINC,
LPC,
PCINC,
DRW,
CM,
S,
SEL
inputwireSWC;
inputwireSWB;
inputwireSWA;
inputwireC;
inputwireZ;
inputwireINT;
inputwireT3;
inputwireCLR_;
inputwire[7:
outputwirePCADD;
outputwireSELCTL;
outputwireINTEN;
outputwireINTDI;
outputwireLIAR;
outputwireIABUS;
outputwireMBUS;
outputwireSBUS;
outputwireABUS;
outputwireM;
outputwireCIN;
outputwireLDC;
outputwireLDZ;
outputwireLIR;
outputwireSTOP;
outputwireMEMW;
outputwireLAR;
outputwireARINC;
outputwireLPC;
outputwirePCINC;
outputwireDRW;
outputwire[39:
0]CM;
outputwire[3:
0]S;
0]SEL;
0]CM_ALTERA_SYNTHESIZED;
0]SYNTHESIZED_WIRE_0;
0]SYNTHESIZED_WIRE_1;
addrtranb2v_inst1(
.Z(Z),
.INT(INT),
.NuA(CM_ALTERA_SYNTHESIZED[5:
0]),
.P(CM_ALTERA_SYNTHESIZED[10:
6]),
.uA(SYNTHESIZED_WIRE_0));
reg6b2v_inst2(
.CLK(T3),
.D(SYNTHESIZED_WIRE_0),
.DOUT(SYNTHESIZED_WIRE_1));
rom64_40b2v_inst3(
.addr(SYNTHESIZED_WIRE_1),
.q(CM_ALTERA_SYNTHESIZED));
assignPCADD=CM_ALTERA_SYNTHESIZED[39];
assignSELCTL=CM_ALTERA_SYNTHESIZED[38];
assignINTEN=CM_ALTERA_SYNTHESIZED[33];
assignINTDI=CM_ALTERA_SYNTHESIZED[32];
assignLIAR=CM_ALTERA_SYNTHESIZED[31];
assignIABUS=CM_ALTERA_SYNTHESIZED[30];
assignMBUS=CM_ALTERA_SYNTHESIZED[29];
assignSBUS=CM_ALTERA_SYNTHESIZED[28];
assignABUS=CM_ALTERA_SYNTHESIZED[27];
assignM=CM_ALTERA_SYNTHESIZED[26];
assignCIN=CM_ALTERA_SYNTHESIZED[21];
assignLDC=CM_ALTERA_SYNTHESIZED[20];
assignLDZ=CM_ALTERA_SYNTHESIZED[19];
assignLIR=CM_ALTERA_SYNTHESIZED[18];
assignSTOP=CM_ALTERA_SYNTHESIZED[17];
assignMEMW=CM_ALTERA_SYNTHESIZED[16];
assignLAR=CM_ALTERA_SYNTHESIZED[15];
assignARINC=CM_ALTERA_SYNTHESIZED[14];
assignLPC=CM_ALTERA_SYNTHESIZED[13];
assignPCINC=CM_ALTERA_SYNTHESIZED[12];
assignDRW=CM_ALTERA_SYNTHESIZED[11];
assignCM=CM_ALTERA_SYNTHESIZED;
assignS[3]=CM_ALTERA_SYNTHESIZED[25];
assignS[2]=CM_ALTERA_SYNTHESIZED[24];
assignS[1]=CM_ALTERA_SYNTHESIZED[23];
assignS[0]=CM_ALTERA_SYNTHESIZED[22];
assignSEL[3]=CM_ALTERA_SYNTHESIZED[37];
assignSEL[2]=CM_ALTERA_SYNTHESIZED[36];
assignSEL[1]=CM_ALTERA_SYNTHESIZED[35];
assignSEL[0]=CM_ALTERA_SYNTHESIZED[34];
Micro_controller.vt
modulemicro_controller_vlg_tst();
regT3;
wireABUS;
wireARINC;
wireCIN;
wireDRW;
wireIABUS;
wireINTDI;
wireINTEN;
wireLAR;
wireLDC;
wireLDZ;
wireLIAR;
wireLIR;
wireLPC;
wireM;
wireMBUS;
wireMEMW;
wirePCADD;
wirePCINC;
wire[3:
wireSBUS;
wireSELCTL;
wireSTOP;
micro_controlleri1(
.ABUS(ABUS),
.ARINC(ARINC),
.CIN(CIN),
.CM(CM),
.DRW(DRW),
.IABUS(IABUS),
.INTDI(INTDI),
.INTEN(INTEN),
.LAR(LAR),
.LDC(LDC),
.LDZ(LDZ),
.LIAR(LIAR),
.LIR(LIR),
.LPC(LPC),
.M(M),
.MBUS(MBUS),
.MEMW(MEMW),
.PCADD(PCADD),
.PCINC(PCINC),
.S(S),
.SBUS(SBUS),
.SEL(SEL),
.SELCTL(SELCTL),
.STOP(STOP),
.T3(T3),
CLR_=0;
T3=0;
#30Z=0;
C=0;
INT=0;
CLR_=1;
SWC=0;
SWA=0;
#20T3=~T3;
for(i=1;
#80IR=i;
end
Micro_controller功能仿真
Reg8.v
modulereg8(T3,DOUT,D);
inputT3;
wireT3;
input[7:
wire[7:
output[7:
reg[7:
always@(posedgeT3)
=D;
reg8.vt
modulereg8_vlg_tst();
wire[7:
reg8i1(
.DOUT(DOUT),
.T3(T3)
D=8'
d0;
#5T3=~T3;
for(i=0;
11;
#10D=i;
reg8.bsf
Reg8功能仿真
Mux2_1.v
modulemux2_1(
d0,
d1,
sel,
dout
);
input[3:
0]d0;
0]d1;
inputsel;
outputdout;
reg[3:
0]dout;
always@(d0ord1orsel)
case(sel)
1'
b0:
dout=d0;
b1:
dout=d1;
endcase
mux2_1.vt
modulemux2_1_vlg_tst();
reg[3:
0]d0;
0]d1;
regsel;
0]dout;
mux2_1i1(
.d0(d0),
.d1(d1),
.dout(dout),
.sel(sel)
d0=4'
b0001;
d1=4'
b1110;
while
(1)
2;
#50sel=i;
mux2_1.bsf
Mux2_1功能仿真
Ucu_ir.bdf
Ucu_ir.bsf
(1)ADD-SUB-AND-INC指令,2个CPU周期
Testbench
moduleucu_ir_vlg_tst();
0]INS;
wire[1:
0]RD;
0]RS;
ucu_iri1(
.INS(INS),
.LDZ(LD
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