XC4VLX1510SF363IWord格式.docx
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XC4VLX1510SF363IWord格式.docx
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Optionalpipelinestages
OptionalprogrammableFIFOlogicautomaticallyremapsRAMsignalsasFIFOsignals
-High-speedmemoryinterfacesupportsDDRandDDR-2SDRAM,QDR-II,andRLDRAM-II.
Table1:
Virtex-4FPGAFamilyMembers
•SelectIO™Technology
-1.5Vto3.3VI/Ooperation
-Built-inChipSync™source-synchronoustechnology
-Digitallycontrolledimpedance(DCI)activetermination
-FinegrainedI/Obanking(configurationinonebank)
•FlexibleLogicResources
•SecureChipAESBitstreamEncryption
•90nmCopperCMOSProcess
•1.2VCoreVoltage
•Flip-ChipPackagingincludingPb-FreePackageChoices
•RocketIO™622Mb/sto6.5Gb/sMulti-GigabitTransceiver(MGT)[FXonly]
•IBMPowerPCRISCProcessorCore[FXonly]
-PowerPC405(PPC405)Core
-AuxiliaryProcessorUnitInterface(UserCoprocessor)
•MultipleTri-ModeEthernetMACs[FXonly]
ConfigurableLogicBlocks(CLBs)
(1)
BlockRAM
Array(3)
Logic
Max
XtremeDSP
PowerPC
RocketIO
Total
Device
Distributed
18Kb
Block
DCMs
PMCDs
Processor
Ethernet
Transceiver
I/O
User
RowxCol
Cells
Slices
RAM(Kb)
Slices
(2)
Blocks
MACs
Banks
XC4VLX15
64x24
13,824
6,144
96
32
48
864
4
N/A
9
320
XC4VLX25
96x28
24,192
10,752
168
72
1,296
8
11
448
XC4VLX40
128x36
41,472
18,432
288
64
1,728
13
640
XC4VLX60
128x52
59,904
26,624
416
160
2,880
XC4VLX80
160x56
80,640
35,840
560
80
200
3,600
12
15
768
XC4VLX100
192x64
110,592
49,152
240
4,320
17
960
XC4VLX160
192x88
152,064
67,584
1056
5,184
XC4VLX200
192x116
200,448
89,088
1392
336
6,048
©
Copyright2004–2010Xilinx,Inc.XILINX,theXilinxlogo,Virtex,Spartan,ISE,andotherdesignatedbrandsincludedhereinaretrademarksofXilinxintheUnitedStatesandothercountries.ThePowerPCnameandlogoareregisteredtrademarksofIBMCorp.andusedunderlicense.Allothertrademarksarethepropertyoftheirrespectiveowners.
DS112(v3.1)August30,2010
ProductSpecification1
Virtex-4FPGAFamilyMembers(Continued)
XC4VSX25
64x40
23,040
10,240
128
2,304
XC4VSX35
96x40
34,560
15,360
192
3,456
XC4VSX55
128x48
55,296
24,576
384
512
5,760
XC4VFX12
12,312
5,472
86
36
648
1
2
XC4VFX20
64x36
19,224
8,544
134
68
1,224
XC4VFX40
96x52
41,904
18,624
291
144
2,592
XC4VFX60
56,880
25,280
395
232
4,176
16
576
XC4VFX100
160x68
94,896
42,176
659
376
6,768
20
XC4VFX140
192x84
142,128
63,168
987
552
9,936
24
896
Notes:
1.OneCLB=FourSlices=Maximumof64bits.
2.EachXtremeDSPslicecontainsone18x18multiplier,anadder,andanaccumulator
3.Someoftherow/columnarrayisusedbytheprocessorsintheFXdevices.
SystemBlocksCommontoAllVirtex-4Families
XesiumClockTechnology
•UptotwentyDigitalClockManager(DCM)modules
-Precisionclockdeskewandphaseshift
-Flexiblefrequencysynthesis
-Dualoperatingmodestoeaseperformancetrade-offdecisions
-Improvedmaximuminput/outputfrequency
-Improvedphaseshiftingresolution
-Reducedoutputjitter
-Low-poweroperation
-Enhancedphasedetectors
-Widephaseshiftrange
•CompanionPhase-MatchedClockDivider(PMCD)blocks
•Differentialclockingstructureforoptimizedlow-jitterclockingandprecisedutycycle
•32GlobalClocknetworks
•RegionalI/OandLocalclocks
FlexibleLogicResources
•Upto40%speedimprovementoverpreviousgenerationdevices
•Upto200,000logiccellsincluding:
-Upto178,176internalregisterswithclockenable(XC4VLX200)
-Upto178,176look-uptables(LUTs)
-LogicexpandingmultiplexersandI/Oregisters
•Cascadablevariableshiftregistersordistributedmemorycapability
500MHzXtremeDSPSlices
•Dedicated18-bitx18-bitmultiplier,multiply-accumulator,ormultiply-adderblocks
•Optionalpipelinestagesforenhancedperformance
•Optional48-bitaccumulatorformultiplyaccumulate(MACC)operation
•Integratedadderforcomplex-multiplyormultiply-addoperation
•CascadeableMultiplyorMACC
•Upto100%speedimprovementoverpreviousgenerationdevices.
500MHzIntegratedBlockMemory
•Upto10Mbofintegratedblockmemory
•Optionalpipelinestagesforhigherperformance
•Multi-rateFIFOsupportlogic
-FullandEmptyFlagsupport
-FullyprogrammableAFandAEFlags
-Synchronous/AsynchronousOperation
•Dual-portarchitecture
•Independentreadandwriteportwidthselection(RAMonly)
•18Kbitblocks(memoryandparity/sidebandmemorysupport)
•Configurationsfrom16Kx1to512x36(4Kx4to512x36forFIFOoperation)
•Byte-writecapability(connectiontoPPC405,etc.)
•Dedicatedcascaderoutingtoform32Kx1memorywithoutusingFPGArouting
ProductSpecification2
SelectIOTechnology
•Upto960userI/Os
•WideselectionsofI/Ostandardsfrom1.5Vto3.3V
•Extremelyhigh-performance
-600Mb/sHSTL&
SSTL(onallsingle-endedI/O)
-1Gb/sLVDS(onalldifferentialI/Opairs)
•Truedifferentialtermination
•Selectedlow-capacitanceI/Osforimprovedsignalintegrity
•SameedgecaptureatinputandoutputI/Os
•MemoryinterfacesupportforDDRandDDR-2SDRAM,QDR-II,andRLDRAM-II.
DigitallyControlledImpedance(DCI)
ActiveI/OTermination
•Optionalseriesorparalleltermination
•Temperaturecompensation
Configuration
•256-bitAESbitstreamdecryptionprovidesintellectualproperty(IP)security
•Improvedbitstreamerrordetection/correctioncapability
•FastSelectMAPconfiguration
•JTAGsupport
•Readbackcapability
ChipSyncTechnology
•IntegratedwithSelectIOtechnologytosimplifysource-synchronousinterfaces
•Per-bitdeskewcapabilitybuiltinallI/Oblocks(variableinputdelayline)
•DedicatedI/Oandregionalclockingresources(pinandtrees)
•Builtindataserializer/deserializerlogicinallI/Oandclockdividers
•Memory/Networking/Telecommunicationinterfacesupto1Gb/s+DDR
90nmCopperCMOSProcess
1.2VCoreVoltage
Flip-ChipPackaging
•Pb-Freepackagesavailablewithproductiondevices.
SystemBlocksSpecifictotheVirtex-4FXFamily
RocketIOMulti-GigabitTransceiver(MGT)
•Full-duplexserialtransceiver(MGT)capableof622Mb/sto6.5Gb/sbaudrates
•8B/10B,64B/66B,
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