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AbstractAbstract|Figures/TablesFigures/Tables|ReferencesReferences
Abstract
Futureembeddedsystemsdemandmulti-processordesignstomeetreal-timedeadlines.Thelargenumberofapplicationsinthesesystemsgeneratesanexponentialnumberofuse-cases.Thekeydesignautomationchallengesaredesigningsystemsfortheseuse-casesandfastexplorationofsoftwareandhardwareimplementationalternativeswithaccurateperformanceevaluationoftheseuse-cases.Thesechallengescannotbeovercomebycurrentdesignmethodologieswhicharesemi-automated,timeconsuminganderrorprone.
Inthispaper,wepresentafullyautomateddesignflowtogeneratecommunicationassist(CA)basedmulti-processorsystems(CA-MPSoC).Aworst-caseperformancemodelofourCAisproposedsothattheperformanceoftheCA-basedplatformcanbeanalyzedbeforeitsimplementation.Thedesignflowprovidesperformanceestimatesandtimingguaranteesforbothhardreal-timeandsoftreal-timeapplications,providedthetasktoprocessormappingsaregivenbytheuser.Theflowautomaticallygeneratesasuper-sethardwarethatcanbeusedinalluse-casesoftheapplications.Thesoftwareforeachoftheseuse-casesisalsogeneratedincludingtheconfigurationofcommunicationarchitectureandinterfacingwithapplicationtasks.
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ArticleOutline
1.Introduction
2.Relatedwork
2.1.Communicationassist
2.2.Designflowsforplatformgeneration
2.3.Performanceanalysis
3.Architecturetemplate
3.1.Processingelement
3.2.Memories
3.3.Communicationassist
4.SDFgraphs
5.SDFmodelofCA
6.Performanceanalysis
6.1.Average-caseanalysis
6.2.Worst-caseanalysis
7.Designflow
7.1.H/Wgeneration
7.2.S/Wgeneration
8.Toolimplementation
9.Experimentsandresults
9.1.Reallifeapplications
9.2.Supportformultipleuse-casesanduse-casemerging
10.Conclusion
References
Vitae
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Intheongoingquestforgreatercomputationalpower,efficientlyexploitingparallelismisofparamountimportance.Architecturaltrendshaveshiftedfromimprovingsingle-threadedapplicationperformance,oftenachievedthroughinstructionlevelparallelism(ILP),toimprovingmultithreadedapplicationperformancebysupportingthreadlevelparallelism(TLP).Thus,multi-coreprocessorsincorporatingtwoormorecoresonasinglediehavebecomeubiquitous.Toachieveconcurrentexecutiononmulti-coreprocessors,applicationsmustbeexplicitlyrestructuredtoexploitparallelism,eitherbyprogrammersorcompilers.However,multithreadedparallelprogrammingmayintroduceoverheadduetocommunicationsamongthreads.Thoughsomeresourcesaresharedamongprocessorcores,currentmulti-coreprocessorsprovidenoexplicitcommunicationssupportformultithreadedapplicationsthattakesadvantageoftheproximitybetweencores.Currently,inter-corecommunicationsdependoncachecoherence,resultingindemand-basedcachelinetransferswiththeirinherentlatencyandoverhead.Inthispaper,weexploretwoapproachestoimprovecommunicationssupportformultithreadedapplications.Prepushingisasoftwarecontrolleddataforwardingtechniquethatsendsdatatodestination’scachebeforeitisneeded,eliminatingcachemissesinthedestination’scacheaswellasreducingthecoherencetrafficonthebus.SoftwareControlledEviction(SCE)improvesthreadcommunicationsbyplacingshareddatainsharedcachessothatitcanbefoundinamuchcloserlocationthanremotecachesormainmemory.Simulationresultsshowsignificantperformanceimprovementwiththeadditionofthesearchitectureoptimizationstomulti-coreprocessors.
2.Threadcommunicationsapproaches
2.1.Prepushing
2.1.1.Motivation
2.1.2.Implementation
2.2.Softwarecontrolledeviction
2.2.1.Motivation
2.2.2.Implementation
2.3.Raceconditions
2.4.Hardwarerealization
3.Performanceestimation
3.1.Benchmarks
3.1.1.ARC4streamcipher
3.1.2.Finite-differencetime-domainmethod
3.1.3.Pingpongbenchmark
3.1.4.Redblackequationsolver
3.2.Prepushing
3.3.Softwarecontrolledeviction
4.Performanceevaluation
5.Relatedwork
6.Conclusion
Researchhighlights
►Multi-coreprocessorsdonotprovideexplicitcommunicationssupportformultithreadedapplications,resultingindatacoherencetrafficandcachemisses.►Prepushingreducesdatacoherencetrafficandeliminatesmissesindestinationcaches.►SoftwareControlledEvictionimprovesthreadcommunicationsbyplacingshareddatainsharedcaches.►Simulationresultsshowsignificantperformanceimprovement.►Bothapproachesprovidethesameexecutiontimeimprovement,butperformdifferentlyintermsofcachemissesanddatarequests.
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