vhdl课程设计gsm通讯机Word格式文档下载.docx
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vhdl课程设计gsm通讯机Word格式文档下载.docx
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INTEGER:
=163;
--163for9600Baud
--81for19200baud
--27for27600baud
--CNT_RS232=50M/16/BAUD/2
CNT_VGA:
INTEGER:
=1
);
PORT(
CLK:
INSTD_LOGIC;
CLK_RS232:
OUTSTD_LOGIC;
CLK_VGA:
OUTSTD_LOGIC
);
ENDENTITY;
ARCHITECTUREFREQUENCY_DIVOFFREQUENCYIS
BEGIN
PROCESS(CLK)
VARIABLEREG_RS232:
STD_LOGIC:
='
0'
;
--REG_DATA
VARIABLEREG_VGA:
VARIABLETEMP_RS232:
INTEGERRANGE0TOCNT_RS232;
--COUNT
VARIABLETEMP_VGA:
INTEGERRANGE0TOCNT_VGA;
BEGIN
IF(CLK'
EVENTANDCLK='
1'
)THEN
TEMP_RS232:
=TEMP_RS232+1;
--VARIABLE_CHANGEING
TEMP_VGA:
=TEMP_VGA+1;
IF(TEMP_RS232=CNT_RS232)THEN--NEEDEDFREQUENCIES
REG_RS232:
=NOTREG_RS232;
TEMP_RS232:
=0;
CLK_RS232<
=REG_RS232;
ENDIF;
IF(TEMP_VGA=CNT_VGA)THEN
REG_VGA:
=NOTREG_VGA;
TEMP_VGA:
CLK_VGA<
=REG_VGA;
ENDIF;
ENDPROCESS;
ENDARCHITECTURE;
模块2:
PS/2Keyboard
接收键盘的时钟源PS2_CLK,并进行平滑处理,接收完一个按键相应输出按键的通码MakeCode和触发信号TRIG,另外输出平滑后的键盘时钟信号PS2_CLKsm,为接收模块提供同步时钟。
具体代码:
libraryieee;
useieee.std_logic_1164.all;
entityPS2keyboardis
port(CLK,PS2_CLK,PS2_DATA:
instd_logic;
TRIG:
outstd_logic;
MAKE_CODE:
outstd_logic_vector(7downto0);
PS2_CLKsm:
outstd_logic
);
endentity;
architecturecodeofPS2keyboardis
typestate_typeis(S1,S2);
typecache_typeisarray(2downto0)ofstd_logic_vector(7downto0);
signalsmooth_ps2_clk:
std_logic;
begin
smooth:
process(CLK)
variablecnt:
integerrange0to7;
variablescan:
std_logic_vector(7downto0);
begin
iffalling_edge(CLK)then
scan(cnt):
=PS2_CLK;
ifcnt=7thencnt:
elsecnt:
=cnt+1;
endif;
ifscan="
11111111"
thensmooth_ps2_clk<
elsifscan="
00000000"
endif;
endprocesssmooth;
receive:
process(smooth_ps2_clk)
integerrange0to10;
variablecount:
integerrange0to2;
variablepstate:
state_type;
variablecache:
cache_type;
variablereg:
std_logic_vector(10downto0);
iffalling_edge(smooth_ps2_clk)then
reg(cnt):
=PS2_DATA;
ifcnt=10then
cnt:
ifcount=1andreg(8downto1)/=X"
F0"
thencount:
endif;
cache(count):
=reg(8downto1);
ifcount=0then--产生TRIG触发信号,下降沿读取,要保证下降沿前后的
--数据保持稳定不变
count:
=count+1;
MAKE_CODE<
=cache(0);
TRIG<
elsifcount=2then
else
count:
TRIG<
MAKE_CODE<
endprocessreceive;
PS2_CLKsm<
=smooth_ps2_clk;
endarchitecture;
模块3:
UART模块
分为发送模块和接收模块。
发送模块由DATA_IN接收数据,由SEND_MARK触发,将数据从TXD发送出去。
接收模块采用16倍频采样,确保不会出现误判,从RXD接收完数据后,触发RECE_MARK信号,将接收到的数据从DATA_OUT输送出去。
entityuart_withoutParityis
port(CLK_UART:
instd_logic;
TXD:
RXD:
SEND_MARK:
RECE_MARK:
--'
whenfinishedreceiving
DATA_IN:
instd_logic_vector(7downto0);
--senddata
DATA_OUT:
outstd_logic_vector(7downto0)--receivedata
architecturecodeofuart_withoutParityis
typesend_stateis(S1,S2,S3,S4);
typerece_stateis(R0,R1,R2);
send:
process(CLK_UART)
variablesamp:
integerrange0to16:
variabletemp:
std_logic_vector(7downto0);
integerrange0to8:
variablesp_state:
send_state;
--presentstateofsendingprocess
if(CLK_UART'
eventandCLK_UART='
)then
casesp_stateis
--Idle
whenS1=>
txd<
samp:
ifSEND_MARK='
then
sp_state:
=S2;
elsesp_state:
=S1;
--startbit
whenS2=>
temp:
=DATA_IN;
=samp+1;
ifsamp=16then
=S3;
else
--data
whenS3=>
=temp(0);
&
temp(7downto1);
ifcnt=8thensp_state:
=S4;
--stopbit
whenS4=>
ifsamp=15then
whenothers=>
endcase;
endif;
endprocesssend;
receive:
variablerp_state:
rece_state;
--presentstateofreceivingprocess
std_logic_vector(7downto0);
integerrange0to16;
integerrange0to8;
ifCLK_UART'
caserp_stateis
--Idle
whenR0=>
RECE_MARK<
reg:
=(others=>
'
);
ifRXD='
then
cnt:
ifcnt=8then
rp_state:
=R1;
endif;
elsecnt:
--receivingdataandparity,totally8bits
whenR1=>
ifcnt=16thencnt:
ifcnt=8then--x16timessampling,getthe8thvalue
reg:
=RXD&
reg(7downto1);
ifcount=8thencount:
cnt:
rp_state:
=R2;
--finishreceivingandoutput
whenR2=>
DATA_OUT<
=reg(7downto0);
--finished
=R0;
whenothers=>
rp_state:
endprocessreceive;
模块4:
VGA接口
接口连接图如下:
VGA模块由3个子模块组成,分别是CONTENT、VGA、VGA_DIV,其中VGA_DIV模块将显示器分割成20*15个小块,VGA模块输出信号至显示器,CONTENT模块包含了所要显示的内容,还包括了键盘按键的判断、UART的缓存数据,还是整个系统主要的状态控制器。
将这3个模块用component语句进行例化,生成VGA_interface模块,再在顶层的BlockDiagram文件进行调用,减少了顶层文件连线的复杂性。
整合后的VGA主控模块VGA_interface如下图:
具体代码如下(不含主控部分):
entityVGAis
port(
HS,VS:
RGB:
outstd_logic_vector(2downto0);
RGB_DATA:
instd_logic_vector(2downto0);
RGB_H:
inoutstd_logic;
RGB_V:
inoutstd_logic
architectureVGA_DISofVGAis
signalh_cnt:
integerrange0to800:
signalv_cnt:
integerrange0to525:
begin
p1:
process(CLK_VGA)
ifrising_edge(CLK_VGA)then
--takeeffectthenextperiod
ifh_cnt=799thenh_cnt<
ifv_cnt=524thenv_cnt<
else
v_cnt<
=v_cnt+1;
if(v_cnt>
36andv_cnt<
=516)thenRGB_V<
=notRGB_V;
--readytodrawarank
elsenull;
endif;
endif;
h_cnt<
=h_cnt+1;
if(h_cnt>
151andh_cnt<
=791)thenRGB_H<
=notRGB_H;
--readytodrawarow
elsenull;
endprocessp1;
p2:
ifrising_edge(CLK_VGA)then
if(h_cnt>
=8andh_cnt<
=103)thenHS<
elseHS<
if(v_cnt>
=2andv_cnt<
=3)thenVS<
elseVS<
endprocessp2;
p3:
ifrising_edge(CLK_VGA)then
if(v_cnt>
=37andv_cnt<
=516)then--480row
=152andh_cnt<
=791)then--640pix
RGB<
=RGB_DATA;
elseRGB<
="
000"
elsenull;
elsenull;
endprocessp3;
end;
entityVGA_DIVis
RGB_H,RGB_V:
x:
inoutintegerrange0to16:
y:
div_x:
inoutintegerrange0to19:
div_y:
inoutintegerrange0to14:
=0
architectureVGA_CONofVGA_DIVis
integerrange0to240:
integerrange0to320:
cnt1:
process(RGB_H)--bothrisingandfallingedge
ifrising_edge(RGB_H)then
h_cnt<
x<
=x+1;
--16*16matrix
ifh_cnt=319thenh_cnt<
elsenull;
if(((h_cnt+1)mod16)=0)then
div_x<
=div_x+1;
x<
--newmatrix
if(div_x=19)thendiv_x<
elsenull;
--16*12
endprocesscnt1;
cnt2:
process(RGB_V)--bothrisingandfallingedge
begin
ifrising_edge(RGB_V)then
v_cnt<
y<
=y+1;
--16*16matrix
ifv_cnt=239thenv_cnt<
if(((v_cnt+1)mod16)=0)then
div_y<
=div_y+1;
y<
--newmatrix
if(div_y=14)thendiv_y<
endprocesscnt2;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
useieee.STD_LOGIC_ARITH.ALL;
entityCONTENTis
CLK,CLK_RS232READ:
SEND_MARK:
UART_value:
outstd_logic_vector(7downto0);
--WRITE_X:
inintegerrange0to19;
--WRITE_Y:
inintegerrange0to14;
WRITE_TR:
DATA_IN:
inintegerrange0to127;
PS2_CLKsm:
RECE_MARK:
UART_in:
instd_logic_vector(7downto0);
DIV_X:
DIV_Y:
X:
Y:
inout
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