交通灯设计Word文件下载.docx
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- 上传时间:2023-01-08
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交通灯设计Word文件下载.docx
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可参照光盘中提供的示例程序。
4、编写完VHDL程序后,保存起来。
(1)-jtdkz.vhd
libraryieee;
useieee.std_logic_1164.all;
entityjtdkzis
port(clk,sm,sb:
instd_logic;
mr,my0,mg0,br,by0,bg0:
outstd_logic);
endentityjtdkz;
architectureartofjtdkzis
typestate_typeis(A,B,C,D);
signalstate:
state_type;
begin
cnt:
process(clk)is
variables:
integerrange0to45;
variableclr,en:
bit;
begin
if(clk'
eventandclk='
1'
)then
ifclr='
0'
thens:
=0;
elsifen='
thens:
=s;
elses:
=s+1;
endif;
casestateis
whenA=>
mr<
='
;
my0<
mg0<
br<
by0<
bg0<
if(sbandsm)='
then
ifs=45thenstate<
=B;
clr:
en:
elsestate<
=A;
elsif(sband(notsm))='
thenstate<
=B;
whenB=>
ifs=5thenstate<
=C;
whenC=>
ifs=25thenstate<
=D;
elsifsb='
thenstate<
=D;
whenD=>
endcase;
endprocesscnt;
endarchitectureart;
(2)cskz.vhd
useieee.std_logic_unsigned.all;
entitycskzis
port(ina:
outa:
endentitycskz;
architectureartofcskzis
process(ina)is
ifina='
thenouta<
elseouta<
endif;
endprocess;
endarchitectureart;
(3)—cnt45s.vhd
libraryieee;
entitycnt45sis
port(sb,clk,en45:
dout45m,dout45b:
outstd_logic_vector(7downto0));
endentitycnt45s;
architectureartofcnt45sis
signalcnt6b:
std_logic_vector(5downto0);
process(sb,clk,en45)is
begin
ifsb='
thencnt6b<
=cnt6b-cnt6b-1;
elsif(clk'
ifen45='
=cnt6b+1;
elsifen45='
thencnt6b<
endprocess;
process(cnt6b)is
casecnt6bis
when"
000000"
=>
dout45m<
="
01000101"
dout45b<
01010000"
000001"
01000100"
01001001"
000010"
01000011"
01001000"
000011"
01000010"
01000111"
000100"
01000001"
01000110"
000101"
01000000"
000110"
00111001"
000111"
00111000"
001000"
00110111"
001001"
00110110"
001010"
00110101"
001011"
00110100"
01101001"
001100"
00110011"
001101"
00110010"
001110"
00110001"
001111"
00110000"
010000"
00101001"
010001"
00101000"
010010"
00100111"
010011"
00100110"
010100"
00100101"
010101"
00100100"
010110"
00100011"
010111"
00100010"
011000"
00100001"
011001"
00100000"
011010"
00011001"
011011"
00011000"
011100"
00010111"
011101"
00010110"
011110"
00010101"
011111"
00010100"
100000"
00010011"
100001"
00010010"
100010"
00010001"
100011"
00010000"
100100"
00001001"
100101"
00001000"
100110"
00000111"
100111"
00000110"
101000"
00000101"
101001"
00000100"
101010"
00000011"
101011"
00000010"
101100"
00000001"
whenothers=>
00000000"
endcase;
(4)cnt05s.vhd
entitycnt05sis
port(clk,en05m,en05b:
dout5:
endentitycnt05s;
architectureartofcnt05sis
signalcnt3b:
std_logic_vector(2downto0);
process(clk,en05m,en05b)is
ifen05m='
thencnt3b<
=cnt3b+1;
elsifen05b='
=cnt3b-cnt3b-1;
process(cnt3b)is
casecnt3bis
000"
dout5<
001"
010"
011"
100"
(5)—cnt25s.vhd
entitycnt25sis
port(sb,sm,clk,en25:
dout25m,dout25b:
endentitycnt25s;
architectureartofcnt25sis
signalcnt5b:
std_logic_vector(4downto0);
process(sb,sm,clk,en25)is
ifsb='
thencnt5b<
=cnt5b-cnt5b-1;
elsifsm='
thencnt5b<
)then
ifen25='
=cnt5b+1;
elsifen25='
process(cnt5b)is
casecnt5bis
when"
00000"
dout25b<
dout25m<
00001"
00010"
00011"
00100"
00101"
00110"
00111"
01000"
01001"
01010"
01011"
01100"
01101"
01110"
01111"
10000"
10001"
10010"
10011"
10100"
10101"
10110"
10111"
11000"
whenothers=>
(6)—xskz.vhd
entityxskzis
port(en45,en25,en05m,en05b:
ain45m,ain45b,ain25m,ain25b,ain05:
instd_logic_vector(7downto0);
doutm,doutb:
endentityxskz;
architectureartofxskzis
process(en45,en25,en05m,en05b,ain45m,ain45b,ain25m,ain25b,ain05)is
ifen45='
thendoutm<
=ain45m(7downto0);
doutb<
=ain45b(7downto0);
elsifen05m='
=ain05(7downto0);
=ain25m(7downto0);
=ain25b(7downto0);
(7)—ymq.vhd
entityymqis
port(clk:
ain41,ain42,ain43,ain44:
instd_logic_vector(3downto0);
del:
outstd_logic_vector(2downto0);
dout7:
outstd_logic_vector(6downto0));
endentityy
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