杭电计组实验9实现RI型指令的CPU设计实验文档格式.docx
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- 上传时间:2023-01-05
- 格式:DOCX
- 页数:14
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杭电计组实验9实现RI型指令的CPU设计实验文档格式.docx
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.clk(clk),
.ZF(ZF),
.OF(OF),
.F(F),
.M_R_Data(M_R_Data)
);
initialbegin
//InitializeInputs
rst=0;
clk=0;
//Wait100nsforglobalresettofinish
#100;
clk=1;
//Addstimulushere
forever
begin
#50;
clk=~clk;
end
end
endmodule
顶层LED验证模块:
moduleTOP_LED(clk_100MHz,oclk,rst,SW,LED);
inputclk_100MHz;
inputoclk,rst;
input[3:
0]SW;
outputreg[7:
0]LED;
wirerclk;
wireZF,OF;
wire[31:
0]F;
0]M_R_Data;
xiaodoudoudong(clk_100MHz,oclk,rclk);
TOP_RI_CPU(clk_100MHz,rst,rclk,ZF,OF,F,M_R_Data);
always@(*)
begin
case(SW)
3'
b0000:
LED=F[7:
0];
b0001:
LED=F[15:
8];
b0010:
LED=F[23:
16];
b0011:
LED=F[31:
24];
b0100:
LED=M_R_Data[7:
b0101:
LED=M_R_Data[15:
b0110:
LED=M_R_Data[23:
b0111:
LED=M_R_Data[31:
b1111:
beginLED[7:
2]=0;
LED[1]=OF;
LED[0]=ZF;
default:
LED=0;
endcase
顶层RI型指令CPU模块
moduleTOP_RI_CPU(inputrst,inputclk,outputZF,outputOF,output[31:
0]F,output[31:
0]M_R_Data);
wireWrite_Reg;
0]Inst_code;
wire[4:
0]rs;
0]rt;
0]rd;
0]rs_data;
0]rt_data;
0]rd_data;
0]imm_data;
wire[15:
0]imm;
wirerd_rt_s;
wireimm_s;
wireMem_Write;
wirealu_mem_s;
0]W_Addr;
0]W_Data;
0]R_Data_A;
0]R_Data_B;
0]ALU_B;
wire[2:
0]ALU_OP;
pcpc_connect(clk,rst,Inst_code);
OP_YIMAop(Inst_code,ALU_OP,rs,rt,rd,Write_Reg,imm,rd_rt_s,imm_s,rt_imm_s,Mem_Write,alu_mem_s);
assignW_Addr=(rd_rt_s)?
rt:
rd;
assignimm_data=(imm_s)?
{{16{imm[15]}},imm}:
{{16{1'
b0}},imm};
Register_fileR_connect(rs,rt,W_Addr,Write_Reg,W_Data,~clk,rst,R_Data_A,R_Data_B);
assignALU_B=(rt_imm_s)?
imm_data:
R_Data_B;
ALUALU_connect(R_Data_A,ALU_B,F,ALU_OP,ZF,OF);
wireclk_tmp;
wired_outn;
regd_out=0;
assignclk_tmp=clk^d_out;
assignd_outn=~d_out;
always@(posedgeclk_tmp)
d_out<
=d_outn;
RAM_BData_Mem(
.clka(clk_tmp),//inputclka
.wea(Mem_Write),//input[0:
0]wea
.addra(F[5:
0]),//input[5:
0]addra
.dina(R_Data_B),//input[31:
0]dina
.douta(M_R_Data)//output[31:
0]douta
);
assignW_Data=alu_mem_s?
M_R_Data:
F;
PC取指令模块:
modulepc(inputclk,inputrst,output[31:
0]Inst_code);
reg[31:
0]PC;
wire[31:
0]PC_new;
initial
PC<
=32'
h00000000;
Inst_ROMInst_ROM1(
.clka(clk),
.addra(PC[7:
2]),
.douta(Inst_code)
assignPC_new=PC+4;
always@(negedgeclkorposedgerst)
if(rst)
PC=32'
else
PC={24'
h000000,PC_new[7:
0]};
OP指令功能译码模块
moduleOP_YIMA(inst,ALU_OP,rs,rt,rd,Write_Reg,
imm,rd_rt_s,imm_s,rt_imm_s,Mem_Write,alu_mem_s);
input[31:
0]inst;
outputreg[2:
outputreg[4:
outputregWrite_Reg;
outputreg[15:
outputregrd_rt_s;
outputregimm_s;
outputregrt_imm_s;
outputregMem_Write;
outputregalu_mem_s;
//R型指令
if(inst[31:
26]==6'
b000000)
rd=inst[15:
11];
rt=inst[20:
rs=inst[25:
21];
alu_mem_s=0;
Mem_Write=0;
rd_rt_s=0;
rt_imm_s=0;
Write_Reg=(inst[5:
0]==0)?
1'
b0:
b1;
case(inst[5:
0])
6'
b100000:
ALU_OP=3'
b100;
b100010:
b101;
b100100:
b000;
b100101:
b001;
b100110:
b010;
b100111:
b011;
b101011:
b110;
b000100:
b111;
//I型立即数寻址指令
29]==3'
b001)
imm=inst[15:
rt=inst[20:
rs=inst[25:
Mem_Write=0;
rd_rt_s=1;
rt_imm_s=1;
alu_mem_s=0;
Write_Reg=1;
case(inst[31:
26])
b001000:
beginimm_s=1;
b001100:
beginimm_s=0;
b001110:
b001011:
//I型取数/存数指令
if((inst[31:
30]==2'
b10)&
&
(inst[28:
26]==3'
b011))
imm_s=1;
b100011:
beginalu_mem_s=1;
beginMem_Write=1;
Write_Reg=0;
寄存器堆模块:
ModuleRegister_file(R_Addr_A,R_Addr_B,W_Addr,Write_Reg,W_Data,Clk,Reset,R_Data_A,R_Data_B);
input[4:
0]R_Addr_A;
0]R_Addr_B;
inputWrite_Reg;
inputClk;
inputReset;
output[31:
0]REG_Files[0:
31];
reg[5:
0]i;
initial//仿真过程中的初始化
for(i=0;
i<
=31;
i=i+1)
REG_Files[i]=0;
assignR_Data_A=REG_Files[R_Addr_A];
assignR_Data_B=REG_Files[R_Addr_B];
always@(posedgeClkorposedgeReset)
if(Reset)
if(Write_Reg&
W_Addr!
=0)
REG_Files[W_Addr]=W_Data;
end
endmodule
ALU运算模块:
moduleALU(A,B,F,ALU_OP,ZF,OF);
0]A,B;
input[2:
outputregZF,OF;
outputreg[31:
regC32;
OF=1'
b0;
C32=1'
case(ALU_OP)
3'
b000:
F=A&
B;
b001:
F=A|B;
b010:
F=A^B;
b011:
F=~(A^B);
b100:
begin{C32,F}=A+B;
OF=A[31]^B[31]^F[31]^C32;
b101:
begin{C32,F}=A-B;
b110:
if(A<
B)
F=1;
else
F=0;
b111:
F=B<
<
A;
endcase
if(F==0)
ZF=1;
ZF=0;
时钟按键消抖代码:
modulexiaodou(
inputclk_100MHz,
inputBTN,
outputregBTN_Out
regBTN1,BTN2;
wireBTN_Down;
reg[21:
0]cnt;
regBTN_20ms_1,BTN_20ms_2;
wireBTN_Up;
always@(posedgeclk_100MHz)
begin
BTN1<
=BTN;
BTN2<
=BTN1;
assignBTN_Down=(~BTN2)&
BTN1;
//从0到1的跳变
if(BTN_Down)
cnt<
=22'
BTN_Out<
=1'
elsecnt<
=cnt+1'
if(cnt==22'
h20000)BTN_20ms_1<
BTN_20ms_2<
=BTN_20ms_1;
if(BTN_Up)BTN_Out<
assignBTN_Up=BTN_20ms_2&
(~BTN_20ms_1);
//从1到0
二、仿真波形
三、电路图
顶层电路模块
顶层电路内部结构
四、引脚配置(约束文件)
NET"
LED[7]"
LOC=T11;
LED[6]"
LOC=R11;
LED[5]"
LOC=N11;
LED[4]"
LOC=M11;
LED[3]"
LOC=V15;
LED[2]"
LOC=U15;
LED[1]"
LOC=V16;
LED[0]"
LOC=U16;
SW[3]"
LOC=M8;
SW[2]"
LOC=V9;
SW[1]"
LOC=T9;
SW[0]"
LOC=T10;
rst"
LOC=C4;
clk_100MHz"
LOC=V10;
oclk"
LOC=C9;
五、思考与探索
(1)R-I型指令CPU实验结果记录表
序号指令执行结果标志结论
1380112340000_123400正确
2200267890000_678900正确
320039000FFFF_900000正确
4380400100000_001000正确
5008228046789_000000正确
6002530256789_123400正确
7008338049000_000000正确
8004640206789_79BD00正确
900414822,0000_555500正确
1000225022FFFF_AAAB00正确
11206b7fff0000_0FFF00正确
12206c8000FFFF_100000正确
13314dffff0000_AAAB00正确
142c4e67880000_000000正确
152c4f678a0000_000100正确
16ac0c00140000_0FFF00正确
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