VHDL课程设计多功能数字钟.docx
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VHDL课程设计多功能数字钟.docx
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VHDL课程设计多功能数字钟
多
功
能
电
子
时
题目:
多功能数字钟
钟
报
告
一、实验目的
1.学习数字系统设计的自顶向下设计法及控制器的设计。
2.加深利用EDA技术实现数字系统的体会。
二、实验仪器及器件
1.EDA开发软件(Quartus7.2)(1套)2.电脑(1台)
3.实验板(1个)
三、实验要求及设计方案
1.设计一个具有24进制计时、显示、整点报时、时间设置和闹钟功能的数字钟,要求时钟的最小分辨率时间为1s。
2.数字钟的设计方案如下:
系统输入:
mode为计时显示和闹钟定时显示转换输入;set为校时和定时设置的时、分、秒转换输入;k为校时的时、分、秒手动加1输入;4*4矩阵键盘为闹钟设置调节闹钟的时、分、秒、时钟的清零以及暂停;clk40M为板载时钟信号;reset为系统复位信号。
输入信号均由按键和4*4矩阵键盘产生。
系统输出:
七段数码管显示输出;蜂鸣器(bell)声音信号输出(用LED灯代替)。
3.多功能数字钟系统功能的具体描述如下:
计时:
正常工作状态下,每日按24小时计时制计时并显示,蜂鸣器逢整点报时。
校时:
在计时显示状态下,按下“set键”,进入“小时”校时状态,再次按下“set键”,进入“分”校时状态,继续按下“set键”,进入“秒”校时状态,第四次按下“set键”又回复到正常计时显示状态。
1)“小时”校时状态:
进入“小时”校时状态后,显示“小时”的数码管闪烁,每按动“k”键一次,“小时”+1,若不按动“k”键则小时数不变,一直按下“k”键则小时数以4Hz的频率递增计数。
2)“分”校时状态:
进入“分”校时状态后,显示“分”的数码管闪烁,每按动“k”键一次,“分”+1,若不按动“k”键则分数不变,一直按下“k”键则分数以4Hz的频率递增计数。
3)“秒”校时状态:
进入“秒”校时状态后,显示“秒”的数码管闪烁,每按动“k”键一次,“秒”+1,若不按动“k”键则秒数不变,一直按下“k”键则秒数以4Hz的频率递增计数。
整点报时:
蜂鸣器在“59”分钟的第51、53、55、57秒发出频率为512Hz的低音,在“59”秒发出频率为1024Hz的高音,结束时为整点。
显示:
采用6个LED数码管分别显示时、分、秒。
闹钟:
闹钟定时时间到,蜂鸣器发出周期为1s的滴、滴声,持续时间为10秒;闹钟定时显示。
闹钟定时设置:
在闹钟显示状态下,按下“set键”,进入“小时”校时状态,再次按下“set键”,进入“分”校时状态,继续按下“set键”,进入“秒”校时状态,第四次按下“set键”又回复到闹钟显示状态。
闹钟的时、分、秒设置过程和计时设置有所不同,在闹钟闪烁的状态下,可以直接在4*4的矩阵键盘上输入想要调整的时间即可。
计时显示和闹钟显示之间的转换:
按动“mode”键,数字钟将在计时显示和闹钟定时显示之间转换。
4)多功能数字钟系统结构逻辑框图如下:
mode
5)控制器的MDS图如下:
set=1
四、各功能模块的源程序代码:
--fenpin模块
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityfenpinis
port(
clk40M,pause:
instd_logic;
clk1000hz,clk1hz,clk4hz,clk500hz:
outstd_logic
);
endfenpin;
architectureoneoffenpinis
signala:
integerrange0to20970:
=0;
signalclk1000,clk1,clk4,clk500:
std_logic;
signals:
std_logic:
='1';
begin
process(clk40M,pause)
begin
ifrising_edge(clk40M)then
ifa=20970then
clk1000<=notclk1000;a<=0;
elsea<=a+1;
endif;endif;
endprocess;
clk1000hz<=clk1000;
process(clk1000)
variablea1:
integerrange0to249:
=0;
begin
ifrising_edge(clk1000)then
ifa1=249thenclk4<=notclk4;a1:
=0;
elsea1:
=a1+1;
endif;endif;
endprocess;
clk4hz<=clk4;
process(clk1000)
variablea1:
integerrange0to2:
=0;
begin
ifrising_edge(clk1000)then
ifa1=2thenclk500<=notclk500;a1:
=0;
elsea1:
=a1+1;
endif;endif;
endprocess;
clk500hz<=clk500;
process(clk1000)
variablea1:
integerrange0to499:
=0;
begin
ifrising_edge(clk1000)then
ifa1=499thenclk1<=notclk1;a1:
=0;
elsea1:
=a1+1;
endif;endif;
ifrising_edge(pause)then
s<=nots;
endif;
endprocess;
clk1hz<=clk1ands;
endone;
--CONTOR模块
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitycontoris
port(clk,k,set,reset,mode:
instd_logic;
chs,cht,cms,cmt,css,cst,flashh,flashm,flashs,sel_show:
outstd_logic);
endcontor;
architecturecontor_archofcontoris
typestatesis(s0,s1,s2,s3,s4,s5,s6,s7);
signalcurrent_state,next_state:
states;
begin
process(reset,clk,next_state,mode)
begin
if(reset='1')then
current_state<=s0;
elsif(clk'eventandclk='1')then
current_state<=next_state;
endif;
endprocess;
process(current_state,k,set,mode)
begin
casecurrent_stateis
whens0=>
flashh<='0';flashm<='0';flashs<='0';cht<='0';cmt<='0';cst<='0';chs<='0';cms<='0';css<='0';sel_show<='1';
if(mode='1')thennext_state<=s4;
elsif(k='0'andset='1')then
next_state<=s1;
else
next_state<=s0;
endif;
whens1=>
flashh<='1';flashm<='0';flashs<='0';cht<='1';cmt<='0';cst<='0';chs<='0';cms<='0';css<='0';sel_show<='1';
if(set='1')then
next_state<=s2;
else
next_state<=s1;
endif;
whens2=>
flashh<='0';flashm<='1';flashs<='0';cht<='0';cmt<='1';cst<='0';chs<='0';cms<='0';css<='0';sel_show<='1';
if(set='1')then
next_state<=s3;
else
next_state<=s2;
endif;
whens3=>
flashh<='0';flashm<='0';flashs<='1';cht<='0';cmt<='0';cst<='1';chs<='0';cms<='0';css<='0';sel_show<='1';
if(set='1')then
next_state<=s0;
else
next_state<=s3;
endif;
whens4=>
flashh<='0';flashm<='0';flashs<='0';cht<='0';cmt<='0';cst<='0';
chs<='0';cms<='0';css<='0';sel_show<='0';
if(mode='1')then
next_state<=s0;
elsif(k='0'andset='1')then
next_state<=s5;
else
next_state<=s4;
endif;
whens5=>
flashh<='1';flashm<='0';flashs<='0';cht<='0';cmt<='0';cst<='0';
chs<='1';cms<='0';css<='0';sel_show<='0';
if(set='1')then
next_state<=s6;
else
next_state<=s5;
endif;
whens6=>
flashh<='0';flashm<='1';flashs<='0';cht<='0';cmt<='0';
cst<='0';chs<='0';cms<='1';css<='0';sel_show<='0';
if(set='1')then
next_state<=s7;
else
next_state<=s6;
endif;
whens7=>
flashh<='0';flashm<='0';flashs<='1';cht<='0';cmt<='0';
cst<='0';chs<='0';cms<='0';css<='1';sel_show<='0';
If(set='1')then
next_state<=s4;
else
next_state<=s7;
endif;
endcase;
endprocess;
endcontor_arch;
********TIMER模块****
--*************cnt60模块*****
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycnt60is
port(clkin,rst:
instd_logic;
mh,ml:
bufferstd_logic_vector(3downto0);
co:
bufferstd_logic);
endcnt60;
architecturecnt60xofcnt60is
begin
process(clkin)
begin
if(rising_edge(clkin))then
if(mh="0101"andml="1001")then
mh<="0000";co<='1';ml<="0000";
elsif(ml="1001")then
ml<="0000";mh<=mh+1;co<='0';
elseml<=ml+1;co<='0';
endif;
endif;
ifrst='1'then
mh<="0000";ml<="0000";
endif;
endprocess;
endcnt60x;
--********MUX2-1模块********
libraryieee;
useieee.std_logic_1164.all;
entitymux2_1is
port(d0,d1,en:
instd_logic;
sel:
instd_logic;
y:
outstd_logic);
endmux2_1;
architecturemux2_1_archofmux2_1is
begin
process(d0,d1,sel)
begin
if(sel='0')then
y<=d0;
elsif(sel='1'anden='0')then
y<=d1;
endif;
endprocess;
endmux2_1_arch;
--*************cnt24模块*****
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycnt24is
port(clkin,rst:
instd_logic;
mh,ml:
bufferstd_logic_vector(3downto0);
co:
bufferstd_logic);
endcnt24;
architecturecnt24xofcnt24is
begin
process(clkin)
begin
if(rising_edge(clkin))then
if(mh="0010"andml="0011")then
mh<="0000";co<='1';ml<="0000";
elsif(ml="1001")then
ml<="0000";mh<=mh+1;co<='0';
elseml<=ml+1;co<='0';
endif;
endif;
ifrst='1'then
mh<="0000";ml<="0000";
endif;
endprocess;
endcnt24x;
--*************TIMER总的模块*****
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitytimeris
port(rst,chs,f4,cms,k,clk1hz,css:
instd_logic;
hh,hl,mh,ml,sh,sl:
outstd_logic_vector(3downto0)
);
endentity;
architectureoneoftimeris
componentmux2_1is
port(d0,d1,en:
instd_logic;
sel:
instd_logic;
y:
outstd_logic);
endcomponent;
componentcnt60is
port(clkin,rst:
instd_logic;
mh,ml:
bufferstd_logic_vector(3downto0);
co:
bufferstd_logic);
endcomponent;
componentcnt24is
port(clkin,rst:
instd_logic;
mh,ml:
bufferstd_logic_vector(3downto0);
co:
bufferstd_logic);
endcomponent;
signalco1,co2,y1,y2,y3:
std_logic;
begin
U1:
mux2_1portmap(clk1hz,f4,k,css,y1);
U2:
mux2_1portmap(co1,f4,k,cms,y2);
U3:
mux2_1portmap(co2,f4,k,chs,y3);
U4:
cnt60portmap(y1,rst,sh,sl,co1);
U5:
cnt60portmap(y2,rst,mh,ml,co2);
U6:
cnt24portmap(y3,rst,hh,hl);
endone;
――*****************Time_com模块*********
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitytime_comis
port(r,hh,mh,sh,hl,ml:
instd_logic_vector(3downto0);
test,chs,cms,css,f4,k:
instd_logic;
bsg,bmg,bhg,bsd,bmd,bhd:
bufferstd_logic_vector(3downto0);
comout:
outstd_logic);
endtime_com;
architecturetime_comxoftime_comis
signalchoose,choose1,choose2:
std_logic;
begin
com:
process(hh,mh,sh,hl,ml,bhd,bhg,bmg,bmd,bsg)
begin
if(bhg=hhandbhd=hlandbmg=mhandbmd=mlandbsg=sh)then
comout<='1';
else
comout<='0';
endif;
endprocess;
--set:
process(f4)
process(chs)
begin
ifrising_edge(test)then
choose<=notchoose;
ifchs='1'then
ifchoose='1'then
ifr>"0010"then
bhg<="0000";else
bhg<=r;
endif;
endif;
ifchoose='0'then
ifr>"0011"then
bhd<="0000";else
bhd<=r;endif;
endif;
endif;
endif;
endprocess;
process(cms)
begin
ifrising_edge(test)then
choose1<=notchoose1;
ifcms='1'then
ifchoose1='1'then
ifr>"0101"then
bmg<="0000";else
bmg<=r;
endif;
endif;
ifchoose1='0'then
ifr>"1001"then
bmd<="0000";else
bmd<=r;endif;
endif;
endif;
endif;
endprocess;
process(css)
begin
ifrising_edge(test)then
choose2<=notchoose2;
ifcss='1'then
ifchoose2='1'then
ifr>"0101"then
bsg<="0000";else
bsg<=r;
endif;
endif;
ifchoose2='0'then
ifr>"1001"then
bsd<="0000";else
bsd<=r;endif;
endif;
endif;
endif;
endprocess;
endtime_comx;
--*****************Show_contor模块****************************
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityshow_contoris
port(hh,mh,sh,bhh,bmh,bsh,hl,ml,sl,bhl,bml,bsl:
instd_logic_vector(3downto0);
flashh,flashm,flashs,clk1,sel_show:
instd_logic;
sld0,shd1,mld3,mhd4,hld6,hhd7:
outstd_logic_vector(3downto0));
endshow_contor;
architectureshow_contor_archofshow_contoris
begin
process(clk1)
begin
ifsel_show='1'then
sld0<=sl;
shd1<=sh;
mld3<=ml;
mhd4<=mh;
hld6<=hl;
hhd7<=hh;
elsifsel_show='0'then
sld0<=bsl;
shd1<=bsh;
mld3<=bml;
mhd4<=bmh;
hld6<=bhl;
hhd7<=bhh;
endif;
if(clk1='1'andflashs='1')then
sld0<="1111";shd1<="1111";
endif;
if(clk1='1'andflashm='1')then
mld3<="1111";mhd4<="1111";
endif;
if(clk1='1'andflashh='1')then
hld6<="1111";hhd7<="1111";
endif;
endprocess;
endshow_contor_arch;
--****************decode模块代码*********************
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
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