数字时钟数字逻辑课程设计报告.docx
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数字时钟数字逻辑课程设计报告.docx
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数字时钟数字逻辑课程设计报告
数字时钟
班级:
学号:
姓名:
指导老师:
提交日期:
2011年1月8日
一.系统简介:
使用VHDL语言编写程序完成数字时钟的功能设计,利用软件进行编译和仿真,最后利用实验箱实现系统。
二.功能简介:
完成时钟的计时、调整,整点报时等基础功能,完成闹钟的设置、开启和关闭功能,整点报时的开启和关闭功能,完成日期设定和显示功能。
三.总体结构逻辑框图:
四.状态图:
五.各模块电路图及程序:
整体电路连接图:
1.总控制模块:
时钟脉冲分频元件:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitydc4_1clkdmuxis
port(
clk:
instd_logic;
clk1,clk4,clk512:
outstd_logic);
enddc4_1clkdmux;
architectureclkdmuxofdc4_1clkdmuxis
signalc1:
std_logic_vector(9downto0);
begin
process(clk)
begin
ifclk'eventandclk='1'then
c1<=c1+1;
endif;
clk1<=c1(9);clk4<=c1(7);
clk512<=c1(0);
endprocess;
endclkdmux;
模式控制元件:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitydc4_2modeis
port(
clk4,bt_m:
instd_logic;
mode:
outstd_logic_vector(1downto0);
cr1,cr2:
outstd_logic);
enddc4_2mode;
architecturemodeofdc4_2modeis
signalmodx:
std_logic_vector(1downto0);
signalc1,c2:
std_logic;
begin
process(clk4,bt_m)
begin
ifclk4'eventandclk4='1'then
ifbt_m='1'then
modx<=modx+1;c2<='1';
elsec2<='0';
endif;
endif;
ifmodx="00"thenc1<='1';
elsec1<='0';
endif;
mode<=modx;
cr1<=c1;cr2<=c2;
endprocess;
endmode;
调节项目控制元件:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitydc4_2modeis
port(
clk4,bt_m:
instd_logic;
mode:
outstd_logic_vector(1downto0);
cr1,cr2:
outstd_logic);
enddc4_2mode;
architecturemodeofdc4_2modeis
signalmodx:
std_logic_vector(1downto0);
signalc1,c2:
std_logic;
begin
process(clk4,bt_m)
begin
ifclk4'eventandclk4='1'then
ifbt_m='1'then
modx<=modx+1;c2<='1';
elsec2<='0';
endif;
endif;
ifmodx="00"thenc1<='1';
elsec1<='0';
endif;
mode<=modx;
cr1<=c1;cr2<=c2;
endprocess;
endmode;
数码管显示元件:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitydc4_4selis
port(
clk:
instd_logic;
sel:
outstd_logic_vector(2downto0));
enddc4_4sel;
architectureselofdc4_4selis
signalselx:
std_logic_vector(2downto0);
begin
process(clk)
begin
ifclk'eventandclk='1'then
selx<=selx+1;
endif;
endprocess;
sel<=selx;
endsel;
模块波形图:
2.时钟模块:
时钟秒调节元件:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitydc3_1secondis
port(
clk1,clk4,rest,bt_a:
instd_logic;
mode,set:
instd_logic_vector(1downto0);
sco,mcen:
outstd_logic;
clks0,clks1:
outstd_logic_vector(3downto0));
enddc3_1second;
architecturesecondofdc3_1secondis
signals0,s1:
std_logic_vector(3downto0);
signalco,rco,cr:
std_logic;
begin
process(clk1,clk4,rest,bt_a,mode,set)
begin
ifclk4'eventandclk4='1'then
ifmode="01"then
ifrest='1'then
cr<='1';
elsifset="00"andbt_a='1'then
cr<='1';
elsecr<='0';
endif;
endif;
endif;
ifcr='1'then
s0<="0000";s1<="0000";
elsifclk1'eventandclk1='1'then
ifs0="1001"ands1="0101"then
s0<="0000";s1<="0000";co<='1';
elsifs0="1001"then
s0<="0000";s1<=s1+1;co<='0';
elses0<=s0+1;co<='0';
endif;
endif;
ifmode="01"andset="01"andbt_a='1'then
rco<=clk4;mcen<='0';
elserco<=co;mcen<='1';
endif;
endprocess;
clks0<=s0;clks1<=s1;sco<=rco;
endsecond;
时钟分调节元件:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitydc3_1miniteis
port(
sco,mcen,clk4,rest,bt_a:
instd_logic;
mode,set:
instd_logic_vector(1downto0);
mco,hcen:
outstd_logic;
clkm0,clkm1:
outstd_logic_vector(3downto0));
enddc3_1minite;
architectureminiteofdc3_1miniteis
signalm0,m1:
std_logic_vector(3downto0);
signalrco,co,cr:
std_logic;
begin
process(sco,mcen,clk4,rest,bt_a,mode,set)
begin
ifmode="01"andrest='1'then
cr<=rest;
elsecr<='0';
endif;
ifcr='1'then
m0<="0000";m1<="0000";
elsifsco'eventandsco='1'then
ifm0="1001"andm1="0101"then
m0<="0000";m1<="0000";
ifmcen='1'thenco<='1';
elseco<='0';
endif;
elsifm0="1001"then
m0<="0000";m1<=m1+1;co<='0';
else
m0<=m0+1;co<='0';
endif;
endif;
ifmode="01"andset="10"andbt_a='1'then
rco<=clk4;hcen<='0';
elserco<=co;hcen<='1';
endif;
endprocess;
clkm0<=m0;clkm1<=m1;mco<=rco;
endminite;
时钟小时调节元件:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitydc3_1houris
port(
mco,hcen,clk4,rest,bt_a:
instd_logic;
mode,set:
instd_logic_vector(1downto0);
hco,dcen:
outstd_logic;
clkh0,clkh1:
outstd_logic_vector(3downto0));
enddc3_1hour;
architecturehourofdc3_1houris
signalh0,h1:
std_logic_vector(3downto0);
signalrco,co,cr:
std_logic;
begin
process(mco,hcen,clk4,rest,bt_a,mode,set)
begin
ifmode="01"andrest='1'then
cr<=rest;
elsecr<='0';
endif;
ifcr='1'then
h0<="0000";h1<="0000";
elsifmco'eventandmco='1'then
ifh0="1001"andh1="0101"then
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