EDA考试参考程序Word格式.docx
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- 上传时间:2022-12-16
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EDA考试参考程序Word格式.docx
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IFcnt=count_valueTHEN
ELSE
=cnt+1;
endif;
else
IFcnt=0THEN
=count_value;
=cnt-1;
ENDPROCESS;
ledout<
=NOTled;
WITHcntSELECT
led<
="
1111001"
WHEN1,
"
0100100"
WHEN2,
0110000"
WHEN3,
0011001"
WHEN4,
0010010"
WHEN5,
0000010"
WHEN6,
1111000"
WHEN7,
0000000"
WHEN8,
0010000"
WHEN9,
1000000"
WHEN0,
1111111"
WHENothers;
ENDa;
第二题分频器
ENTITYdiv4IS
PORT(clk:
din:
INSTD_LOGIC_VECTOR(3DOWNTO0);
fout:
OUTstd_LOGIC);
ENDdiv4;
ARCHITECTUREaOFdiv4IS
begin
process(clk)
variablecnt:
std_logic_vector(3downto0);
begin
if(clk'
eventandclk='
)then
ifcnt="
1111"
then
cnt:
0000"
;
=cnt+'
ifdin="
fout<
=cnt(3);
elsifdin="
1000"
=cnt
(2);
1100"
=cnt
(1);
1110"
=cnt(0);
='
endprocess;
enda;
第三题
ENTITYdivIS
GENERIC(num:
=2);
PORT
(clk:
co:
OUTSTD_LOGIC);
ENDdiv;
ARCHITECTURErtlOFdivIS
PROCESS(clk)
VARIABLEcnt:
STD_LOGIC_VECTOR(numdownto0);
IF(clk'
ENDIF;
co<
=cnt(num);
ENDrtl;
第四题
COUNT:
SIGNALco:
STD_LOGIC;
count<
=co;
STD_LOGIC_VECTOR(3DOWNTO0);
)then
if(cnt="
=notco;
elsif(cnt=din)then
endrtl;
第五题
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityfenpinis
port(clk:
instd_logic;
en:
instd_logic_vector(1downto0);
cout:
outstd_logic;
outstd_logic_vector(6downto0));
endfenpin;
architecturedgnfenpinoffenpinis
signalled:
std_logic_vector(6downto0);
signalhex:
process(clk)
eventANDclk='
if(en="
00"
if(cnt>
cout<
elsif(en="
01"
1010"
0'
10"
cout<
else
endif;
endprocess;
=notled;
withenselect
when"
0001000"
0001110"
11"
whenothers;
enddgnfenpin;
第六题
PORT(MA,MB:
clk:
OUTSTD_LOGIC_VECTOR(6downto0));
STD_LOGIC_VECTOR(3downto0);
STD_LOGIC_VECTOR(6downto0);
IF(MA='
ANDMB='
IFcnt>
0011"
THEN
ELSIF(MA='
0101"
0111"
1001"
ENDPROCESS;
ledout<
WITHcntSELECT
led<
WHEN"
0001"
0010"
0100"
0110"
WHENothers;
第七题
entitycounteris
port(clk,clk1,en,clr:
co,scanout:
endcounter;
architecturertlofcounteris
signalcnt:
std_logic_vector(7downto0);
signalled:
signalscan:
std_logic;
signalhex:
process(clk,clr)
ifclr='
then
=(others=>
'
);
elsifclk'
ifen='
00001001"
00010000"
elsifcnt="
00011001"
then--注意此处,前面跳过了A到F的计数,所以计数到11001
00000000"
process(clk1)
ifclk1'
eventandclk1='
scan<
=notscan;
scanout<
=scan;
hex<
=cnt(7downto4)whenscan='
elsecnt(3downto0);
withhexselect
第八题序列发生器
entityxulieis
outstd_logic);
endxulie;
architecturefashengqiofxulieis
signalcnt:
std_logic_vector(2downto0);
if(clk'
111"
000"
withcntselect
'
001"
010"
011"
100"
101"
endfashengqi;
第九题
entitycaidengis
port(rl,clk:
ledout:
outstd_logic_vector(15downto0));
endcaideng;
architectureaofcaidengis
std_logic_vector(15downto0);
signalk:
if(k='
=(0=>
1=>
2=>
others=>
k<
elsif(rl='
=led(14downto0)&
led(15);
=led(0)&
led(15downto1);
=led;
第十题
ENTITYshifter1IS
PORT(clk,clr,ser,dir,stld:
din:
INSTD_LOGIC_VECTOR(0TO7);
qh:
ENDshifter1;
ARCHITECTURErt1OFshifter1IS
SIGNALreg:
STD_LOGIC_VECTOR(0TO7);
process(clk,clr)
ifclr='
reg<
elsifclk'
ifstld='
reg<
=din;
if(dir='
=reg(1to7)&
ser;
qh<
=reg(0);
=ser&
reg(0to6);
=reg(7);
endrt1;
第十一题
entityselectoris
port(b:
instd_logic_vector(6downto0);
clr:
red,gree:
endselector;
architecturertlofselectoris
signalcount:
signala:
process(b,clr)
if(clr='
a<
foriin0to6loop
a(i)<
=b(i);
endloop;
process(a)
ifa(i)='
andcnt<
gree<
red<
elsif(cnt>
"
=cnt;
withcountselect
第十二题
ENTITYshifterIS
PORT(clk,clr,ser,stld:
ENDshifter;
ARCHITECTURErt1OFshifterIS
第十三题
ENTITYbhxsIS
PORT(INPUT:
INSTD_LOGIC_VECTOR(15DOWNTO0);
LEDOUT:
outSTD_LOGIC_VECTOR(6DOWNTO0));
ENDbhxs;
ARCHITECTURERT1OFbhxsIS
SIGNALLED:
process(INPUT)
LEDOUT<
=NOTLED;
IF(INPUT(0)='
LED<
ELSIF(INPUT
(1)='
ELSIF(INPUT
(2)='
ELSIF(INPUT(3)='
ELSIF(INPUT(4)='
ELSIF(INPUT(5)='
ELSIF(INPUT(6)='
ELSIF(INPUT(7)='
ELSIF(INPUT(8)='
ELSIF(INPUT(9)='
ELSIF(INPUT(10)=
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