AT89S52 specification5000文档格式.docx
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AT89S52 specification5000文档格式.docx
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256*8-bitInternalRAM
32ProgrammableI/OLines
Three16-bitTimer/Counters
EightInterruptSources
FullDuplexUARTSerialChannel
Low-powerIdleandPower-downModes
InterruptRecoveryfromPower-downMode
WatchdogTimer
DualDataPointer
Power-offFlag
1.Description
TheAT89S52isalow-power,high-performanceCMOS8-bitmicrocontrollerwith8Kbytesofin-systemprogrammableFlashmemory.ThedeviceismanufacturedusingAtmen’shigh-densitynonvolatilememorytechnologyandiscompatiblewiththeindustry-standard80C51instructionsetandpinot.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememoryprogrammer.Bycombiningaversatile8-bitCPUwithin-systemprogrammableFlashonamonolithicchip,theAtmenAT89S52isapowerfulmicrocontrollerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.TheAT89S52providesthefollowingstandardfeatures:
8KbytesofFlash,256bytesofRAM,32I/Olines,Watchdogtimer,twodatapointers,three16-bittimer/counters,asix-vectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillator,andclockcircuitry.Inaddition,theAT89S52isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePower-downmodesavestheRAMcon-tentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenextinterruptorhardwarereset.
2.PinConfigurations
3.PinDescription
3.1VCC
Supplyvoltage.
3.2GND
Ground.
3.3Port0
Port0isan8-bitopendrainbidirectionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashigh-impedanceinputs.
Port0canalsobeconfiguredtobethemultiplexedlow-orderaddress/databusduringaccessestoexternalprogramanddatamemory.Inthismode,P0hasinternalpull-ups.
Port0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesduringprogramverification.Externalpull-upsarerequiredduringprogramverification.
3.4Port1
Port1isan8-bitbidirectionalI/Oportwithinternalpull-ups.ThePort1outputbufferscan
sink/sourcefourTTLinputs.When1sarewrittentoPort1pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups.Inaddition,P1.0andP1.1canbeconfiguredtobethetimer/counter2externalcountinput(P1.0/T2)andthetimer/counter2triggerinput(P1.1/T2EX),respectively,asshowninthefollowingtable.
Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.
PortPin
AlternateFunctions
P1.0
T2(externalcountinputtoTimer/Counter2),clock-out
P1.1
T2EX(Timer/Counter2capture/reloadtriggeranddirectioncontrol)
P1.5
MOSI(usedforIn-SystemProgramming)
P1.6
MISO(usedforIn-SystemProgramming)
P1.7
SCK(usedforIn-SystemProgramming)
3.5Port2
Port2isan8-bitbidirectionalI/Oportwithinternalpull-ups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups.
Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses(MOVX@DPTR).Inthisapplication,Port2usesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVX@RI),Port2emitsthecontentsoftheP2Special
FunctionRegister.
Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.
3.6Port3
Port3isan8-bitbidirectionalI/Oportwithinternalpull-ups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthepull-ups.
Port3receivessomecontrolsignalsforFlashprogrammingandverification.
Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89S52,asshowninthefollowingtable.
3.7RST
Resetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresets
P3.0
RXD(serialinputport)
P3.1
TXD(serialoutputport)
P3.2
INT0(externalinterrupt0)
P3.3
INT1(externalinterrupt1)
P3.4
T0(timer0externalinput)
P3.5
T1(timer1externalinput)
P3.6
WR(externaldatamemorywritestrobe)
P3.7
RD(externaldatamemoryreadstrobe)
thedevice.Thispindriveshighfor98oscillatorperiodsaftertheWatchdogtimesout.TheDISRTObitinSFRAUXR(address8EH)canbeusedtodisablethisfeature.InthedefaultstateofbitDISRTO,theRESETHIGHoutfeatureisenabled.
3.8ALE/PROG
AddressLatchEnable(ALE)isanoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput(PROG)duringFlashprogramming.
Innormaloperation,ALEisemittedataconstantrateof1/6theoscillatorfrequencyandmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskippedduringeachaccesstoexternaldatamemory.
Ifdesired,ALEoperationcanbedisabledbysettingbit0ofSFRlocation8EH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledhigh.SettingtheALE-disablebithasnoeffectifthemicrocontrollerisinexternalexecutionmode.
3.9PSEN
ProgramStoreEnable(PSEN)isthereadstrobetoexternalprogrammemory.
WhentheAT89S52isexecutingcodefromexternalprogrammemory,PSENisactivatedtwiceeachmachinecycle,exceptthattwoPSENactivationsareskippedduringeachaccesstoexternaldatamemory
3.10EA/VPP
ExternalAccessEnable.EAmustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFH.Note,however,thatiflockbit1isprogrammed,EAwillbeinternallylatchedonreset.EAshouldbestrappedtoVCCforinternalprogramexecutions.
Thispinalsoreceivesthe12-voltprogrammingenablevoltage(VPP)duringFlashprogramming.
3.11XTAL1
Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit.
3.12XTAL2
Outputfromtheinvertingoscillatoramplifier.
4.SpecialFunctionRegisters
SpecialFunctionRegister(SFR)thatnotalloftheaddressesareoccupied,andunoccupiedaddressesmaynotbeimplementedonthechip.Readaccessestotheseaddresseswillingeneralreturnrandomdata,andwriteaccesseswillhaveanindeterminateeffect.
Usersoftwareshouldnotwrite1stotheseunlistedlocations,sincetheymaybeusedinfutureproductstoinvokenewfeatures.Inthatcase,theresetorinactivevaluesofthenewbitswillalwaysbe0.
Timer2Registers:
ControlandstatusbitsarecontainedinregistersT2CONandT2MODforTimer2.Theregisterpair(RCAP2H,RCAP2L)aretheCapture/ReloadregistersforTimer2in16-bitcapturemodeor16-bitauto-reloadmode.
InterruptRegisters:
TheindividualinterruptenablebitsareintheIEregister.TwoprioritiescanbesetforeachofthesixinterruptsourcesintheIPregister.
DualDataPointerRegisters:
Tofacilitateaccessingbothinternalandexternaldatamemory,twobanksof16-bitDataPointerRegistersareprovided:
DP0atSFRaddresslocations82H-83HandDP1at84H-85H.BitDPS=0inSFRAUXR1selectsDP0andDPS=1selectsDP1.TheusershouldalwaysinitializetheDPSbittotheappropriatevaluebeforeaccessingtherespectiveDataPointerRegister.
PowerOffFlag:
ThePowerOffFlag(POF)islocatedatbit4(PCON.4)inthePCONSFR.POFissetto“1”duringpowerup.Itcanbesetandrestundersoftwarecontrolandisnotaffectedbyreset.
5.MemoryOrganization
MCS-51deviceshaveaseparateaddressspaceforProgramandDataMemory.Upto64KbyteseachofexternalProgramandDataMemorycanbeaddressed.
5.1ProgramMemory
IftheEApinisconnectedtoGND,allprogramfetchesaredirectedtoexternalmemory.
OntheAT89S52,ifEAisconnectedtoVCC,programfetchestoaddresses0000Hthrough1FFFHaredirectedtointernalmemoryandfetchestoaddresses2000HthroughFFFFHaretoexternalmemory.
5.2DataMemory
TheAT89S52implements256bytesofon-chipRAM.Theupper128bytesoccupyaparalleladdressspacetotheSpecialFunctionRegisters.Thismeansthattheupper128byteshavethesameaddressesastheSFRspacebutarephysicallyseparatefromSFRspace.
Whenaninstructionaccessesaninternallocationaboveaddress7FH,theaddressmodeusedintheinstructionspecifieswhethertheCPUaccessestheupper128bytesofRAMortheSFRspace.InstructionswhichusedirectaddressingaccesstheSFRspace.
Forexample,thefollowingdirectaddressinginstructionaccessestheSFRatlocation0A0H(whichisP2).
MOV0A0H,#data
Instructionsthatuseindirectaddressingaccesstheupper128bytesofRAM.Forexample,thefollowingi
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