东南大学计算结构CPU报告Word文档下载推荐.docx
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东南大学计算结构CPU报告Word文档下载推荐.docx
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Instruction
OPCODE
Comments
ADDX
00000001
ACC+[X]->
ACC
SUBX
00000010
ACC-[X]->
ANDX
00000011
ACCand[X]->
ORX
00000100
ACCor[X]->
NOTX
00000101
NOT[X]->
SHIFTR
00000110
SHIFTACCtoRight1bit,LogicShift
SHIFTL
00000111
SHIFTACCtoLeft1bit,LogicShift
MPYX
00001000
ACC×
[X]->
DIVX
00001001
ACC÷
JMPGEZX
00001010
IfACC≥0thenX->
PCelsePC+1->
PC
JMPX
00001011
X->
HALT
00001100
Haltaprogram
STOREX
00001101
ACC->
[X]
LOADX
00001110
Table1.Listofinstructionsandrelevantopcodes
3.Theoverallconnectionexpressedinthetopmoduleform
Figure2.Theoverallconnectionexpressedinthetopmoduleform
4.InternalRegistersandMemory
4.1Memory(Dist_mem_gen_v7_1)
TheXilinxLogiCORE™IPDistributedMemoryGeneratorcoreusesXilinxSynthesisTechnology(XST)tocreateavarietyofdistributedmemories.Itgeneratesread-onlymemories(ROMs),single,simpledual,anddual-portrandomaccessmemories(RAMs),andSRL16-basedmemories;
Supportsdatadepthsrangingfrom16–65,536words;
Supportsdatawidthsrangingfrom1–1024bits.
ThismemoryisasingleportRAMgeneratedbyDist_mem_gen_v7_1.
4.2MAR(MemoryAddressRegister)
MARcontainsthememorylocationofthewordtobereadfromthememoryorwrittenintothememory.Here,READoperationisdenotedastheCPUreadsfrommemory,andWRITEoperationisdenotedastheCPUwritestomemory.Inourdesign,MARhas8bitstoaccessoneof256addressesofthememory.
4.3MBR(MemoryBufferRegister)
MBRcontainsthevaluetobestoredinmemoryorthelastvaluereadfrommemory.MBRisconnectedtotheaddresslinesofthesystembus.Inourdesign,MBRhas16bits.Themodulehasbeenhorizontallyinverted.
4.4PC(ProgramCounter)
PCkeepstrackoftheinstructionstobeusedintheprogram.Inourdesign,PChas8bits.
4.5IR(InstructionRegister)
IRcontainstheopcodepartofaninstruction.Inourdesign,IRhas8bits.
4.6ACC(Accumulator)
ACCholdsoneoperandforALU,andgenerallyACCholdsthecalculationresultofALU.Inourdesign,ACChas16bits.BRisusedasaninputofALU,itholdsotheroperandforALU.Inourdesign,BRhas16bits.Themodulehasbeenhorizontallyinverted.
4.7ALU(ArithmeticLogicUnit)
ALUisacalculationunitwhichaccomplishesbasicarithmeticandlogicoperations.Inourdesign,someoperationsmustbesupportedwhicharelistedasfollows:
Table2.ALUOperations
4.8CU(MicroprogrammedControlUnit)
WehavelearnttheknowledgeofMicroprogrammedcontrolunit.Here,weonlyreviewsometermsandbasicstructures.
IntheMicroprogrammedcontrol,themicroprogramconsistsofsomemicroinstructionsandthemicroprogramisstoredincontrolmemorythatgeneratesallthecontrolsignalsrequiredtoexecutetheinstructionsetcorrectly.Themicroinstructioncontainssomemicro-operationswhichareexecutedatthesametime.
Figure3showsthekeyelementsofsuchanimplementation.Thesetofmicroinstructionsisstoredinthecontrolmemory.Thecontroladdressregistercontainstheaddressofthenextmicroinstructionstoberead.Whenamicroinstructionisreadfromthecontrolmemory,itistransferredtoacontrolbufferregister.Theregisterconnectstothecontrollinesemanatingfromthecontrolunit.Thus,readingamicroinstructionfromthecontrolmemoryisthesameasexecutingthatmicroinstruction.Thethirdelementshowninthefigureisasequencingunitthatloadsthecontroladdressregisterandissuesareadcommand.
Figure3.ControlUnitMicro-architecture
Inmydesign,IsimplifythestructureofMU.Figure4showstheControlUnitMicro-architectureinmydesign.CMisaDistributedROMgeneratedbyDist_mem_gen_v7_1.Itsfunctionisthesamewiththecontrolmemoryplusthecontrolbufferregisterinfigure3.Similarly,theSequencingLogic’sfunctionisthesamewithsequencinglogicpluscontroladdressregisterinfigure3.
Figure4.ControlUnitMicro-architectureinmydesign
ControlSignals
CM地址控制
C0
CAR<
=CAR+1
C1
=***
C2
=0
系统总线
C3
RWmemory
C5
Wmemory
数据通路
C4
memory<
=MBR
C6
MBR<
=memory
C7
IR<
=MBR[15..8]
C8
MAR<
=MBR[7..0]
C9
BR<
C10
PC<
C11
=PC
C12
=PC+1
C13
ALU<
=BR
C14
=ACC
C15
ACC<
=ALU
C16
C17
ALU控制
ALU0
ALU1
ALU2
ALU3
Table3.Meaningsofeachbitofcontrolsignal
运算
ALU[3:
0]
ADD
0001
0010
0011
0100
0101
0110
0111
1000
1001
Table4.MeaningsofALU[3:
0]signal
Table5.CPUinstructionsetandrelevantmicro-operationsandcontrolsignals
Asfigure4andtable3shows,thereare2outputbusfromControlUnit.OneisthecontrolsignalbusCS[17:
0],theotheroneistheALUFlagsignalbusALUFlag[3:
0],whichindicatesthatwhichcalculationisgoingtobeexecutedinALU.Morespecifically,table4showsmeaningsofALU[3:
0]signal.
Table5showstheCPUinstructionsetandaccordinglymicro-operationsandcontrolsignals.Thisisthefoundationofthewholedesign.
5.Designdescriptionofthesimulationinputwaveforms
Twosimulationinputsignalsareneededinmydesign.
(1)clk:
clocksignalofthewholesystem.Theclockperiodis10us.Alltheregistersarepositive-edge-triggered.
(2)reset:
resetwhenreset=1.Alltheresetsignalsfortheregistersaresynchronizedtotheclocksignal.
6.Simulationresults
(1)1+2+3+……+100=5050
Table6.Programof1+2+3+……+100
Figure5.Waveformof1+2+3+……+100
(2)12×
3=36
Table7.Programof12×
3
Figure6.Waveformof12×
(3)12÷
3=4
Table8.Programof12÷
Figure7.Waveformof12÷
7.ConclusionsandDiscussions
(1)Ittakes46mstofinishthecalculation1+2+3+……+100=5050,intheconditionoftheclockperiod10us.
(2)Theresultofthemultiplicationcalculationhasbeenlimitedto8bitsincetheMRregisterisnotused.
(3)Thedivisioncalculationcanonlybeencalledexactdivision,sincetheoperatorwhichisusedinthecodeis“/”.
(4)感想:
CPU的设计相对比较复杂,在真正用ISE进行编程仿真之前需要把课本上CPU部分尤其是CU的工作原理弄清楚,并用EXCEL工具设计自己的指令集和其对应的微操作。
这中间很多地方容易出错,也容易使人迷糊,这时就要勤于动手在纸上规划自己的设计。
当草稿纸上和EXCEL中的设计完成后,再用ISE进行编程仿真就会很快了,良好的设计会对后面的工作起到很大的促进作用。
在这中间会对课本知识有更加透彻深入的理解。
这个实验完全由我独立完成,其中前期设计所使用的时间占到了总花费时间的一半,后期编程调试仿真花费了总时间的另一半。
Appendix
----------MAR----------
moduleMAR(
input[15:
0]MBRdata,
input[7:
0]PCdata,
input[17:
0]CS,
output[7:
0]MA
);
reg[7:
0]MA;
always@(posedgeCS[8]orposedgeCS[11])
begin
if(CS[8]==1)beginMA<
=MBRdata[7:
0];
end
if(CS[11]==1)beginMA<
=PCdata;
end
end
endmodule
----------MBR----------
moduleMBR(
output[15:
0]MBdata,
0]ACC,
0]MEM
reg[15:
0]MBdata;
always@(posedgeCS[6]orposedgeCS[17])
if(CS[6]==1)beginMBdata<
=MEM;
if(CS[17]==1)beginMBdata<
=ACC;
end
-----------PC----------
modulePC(
inputreset,
inputclk,
0]PCdata
0]PCdata;
always@(posedgeclk)
begin
if(reset==1)beginPCdata<
=8'
b00000000;
if(CS[10]==1)beginPCdata<
if(CS[12]==1)beginPCdata<
=PCdata+1;
----------IR----------
moduleIR(
0]IRdata
0]IRdata;
always@(posedgeCS[7])
if(CS[7]==1)beginIRdata<
=MBRdata[15:
8];
----------ACC----------
moduleACC(
0]ALUdata,
0]BRdata,
0]ACCdata,
outputzflag
0]ACCdata;
regzflag;
if(reset==1)
ACCdata<
=16'
b0000000000000000;
zflag<
=1;
elseif(ACCdata[15]==0)
if(CS[15]==1)
=ALUdata;
zflag<
elseif(CS[16]==1)
=BRdata;
elsebeginzflag<
else
z
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