基于FPGA的串口控制器设计外文文献翻译中英文翻译.docx
- 文档编号:1797035
- 上传时间:2022-10-24
- 格式:DOCX
- 页数:20
- 大小:1.09MB
基于FPGA的串口控制器设计外文文献翻译中英文翻译.docx
《基于FPGA的串口控制器设计外文文献翻译中英文翻译.docx》由会员分享,可在线阅读,更多相关《基于FPGA的串口控制器设计外文文献翻译中英文翻译.docx(20页珍藏版)》请在冰豆网上搜索。
基于FPGA的串口控制器设计外文文献翻译中英文翻译
TheserialcontrollerdesignbasedonFPGA
Introduction
Theuseofhardwaredescriptionlanguage(HDL)isbecomingamoredominantfactor,whendesigningandverifyingFPGAdesigns.Theuseofbehaviorleveldescriptionnotonlyincreasesthedesignproductivity,butalsoprovidesuniqueadvantagesinthedesignverification.ThemostdominantHDLstodayarecalledVerilogandVHDL.ThisapplicationnotewillillustratetheuseofVerilogindesignandverificationofadigitalUART(UniversalAsynchronousReceiver&Transmitter).
DefiningtheUART.
TheUARTconsistsoftwoindependentHDLmodules.Onemoduleimplementsthetransmitter,whiletheothermoduleimplementsthereceiver.Thetransmitterandreceivermodulescanbecombinedatthetoplevelofthedesign,foranycombinationsoftransmitterandreceiverchannelsrequired.Datacanbewrittentothetransmitterandreadoutfromthereceiver,allthroughasingle8bitbi-directionalCPUinterface.Addressmappingforthetransmitterandreceiverchannelscaneasilybebuildintotheinterfaceatthetoplevelofthedesign.Bothmodulesshareacommonmasterclockcalledmclkx16.Withineachmodulemclkx16aredivideddowntoindependentbaudrateclocks.
UARTfunctionaloverview.
AbasicoverviewoftheUARTisshownbelow.Atthelefthandsideisshown“transmitholdregister”,“transmitshiftregister”andthetransmitter“controllogic”block,allcontainedwithinthetransmittermodulecalled“txmit”.Attherighthandsideisshownthe“receiveshiftregister”,“receiveholdregister”andthereceiver“controllogic”block,allcontainedwithinthereceivermodulecalled“rxcver”.Thetwomoduleshaveseparateinputsandoutputsformostoftheircontrollines,onlythebi-directionaldatabus,masterclockandresetlinesaresharedbybothmodules.
UARTtimingdiagrams.
Belowisshown,howdatawrittentothe“transmitholdregister”getsloadedintothe“transmitshiftregister”,andattherisingedgeofthebaudrateclock,shiftedtotxoutput.
TheTransmittermodule.
Themasterclockcalledmclkx16aredivideddowntotheproperbaudratecalledtxclkandequalstomclkx16/16.Datawritteninparallelformattothemodulearelatchedinternally,andshiftedinserialformattothetxoutputatthefrequencyofthebaudrateclock.DatashiftedtothetxoutputfollowstheUARTdataformatshowninfig.6.
Behavioraldescriptionofthetransmitter.
Thetransmitterwaitsfornewdatatobewrittentothemodule.Whennewdataarewrittenatransmitsequenceisinitialized.Datathatwaswritteninparalleltothemodulegetstransmittedasserialdataframesatthetxoutput.Whennotransmitsequenceareinplace,thetxoutputisheldhigh.
Implementationofthetransmittermodule.
InternalsignalsinVerilogaredeclaredas“wire”or“reg”datatypes.Signalsofthe“wire”typeareusedforcontinuosassignments,alsocalledcombinatorialstatements.Signalsofthe“reg”typeareusedforassignmentswithintheVerilog“always”block,oftenuseforsequentiallogicassignments,butnotnecessarily.ForfurtherexplanationseeaVerilogreferencebook.Datatypesoftheinternalsignalsofthemodulecanbereferredtointable3.
Wehavenowpassedbyallnecessarydeclarations,andarenowreadytolookattheactualimplementation.Usinghardwaredescriptionlanguageallowsustodescribethefunctionofthetransmitterinamorebehavioralmanner,ratherthanfocusonit’sactualimplementationatgatelevel.
Insoftwareprogramminglanguage,functionsandproceduresbreakslargerprogramsintomorereadable,manageableandcertainlymaintainablepieces.AVerilogfunctionandtaskareusedastheequivalenttomultiplelinesofVerilogcode,wherecertaininputsorsignalsaffectscertainoutputsorvariables.Theuseoffunctionsandtasksusuallytakesplacewheremultiplelinesofcodearerepeatedlyusedinadesign,andhencemakesthedesigneasiertoreadandcertainlymaintain.AVerilogfunctioncanhavemultipleinputs,butalwayshaveonlyoneoutput,whiletheVerilogtaskcanhavebothmultipleinputs,andmultipleoutputs.BelowisshowntheVerilogtask,thatholdallnecessarysequentialstatements,todescribethetransmitterinthe“shift”mode.
Wehereseethetwotagbitscalledtag1andtag2concatenatedtothe“transmitshiftregister.Similartaskswerecreatedtodescribethetransmitterin“idle”and“load”modes.ByusingtheseVerilogtasks,wecannowcreateavery“easytoread”behavioralmodeloftheholetransmitprocess.
Iftxdoneandtxdatardybotharetrue,thetransmitterenterloadmode.Nexttotheloadmode,thetransmitterentersshiftmode.Attherisingedgeofthebaudrateclock,thecontentsoftsrareshiftedtothetxoutput.Paritygenerationtakesplaceduringshiftingofthetsr,asshownbelow.
Simulationofa
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- 基于 FPGA 串口 控制器 设计 外文 文献 翻译 中英文