MicroblazeConfigFPGAWord文档下载推荐.docx
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MicroblazeConfigFPGAWord文档下载推荐.docx
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LISTOFFIGURES3
REVIEW4
HISTORY4
REFERENCEDOCUMENTS5
Abbreviationsanddefinitions6
1.Introduction7
2.Functionaldescription7
2.1Interface7
2.2AccessFPGAregisters8
2.3Example9
3.ModifySystemParameters11
ENDOFDOCUMENT12
LISTOFFIGURES
Figure1TopLevelInterfaceofMicroblazeConfigurationBlock9
Figure2uPinterface:
WriteOperation10
Figure3uPinterface:
ReadOperation11
Figure4ExampleofUsingMicroblaze11
REVIEW
HISTORY
Description
08/07/2008
Creation
REFERENCEDOCUMENTS
[1]XilinxUserguide:
EDKConcepts,Tools,andTechniques
[2]EDK9.1MicroBlazeTutorialinVirtex-4
[3]Xilinx’strainingmaterialsaboutEDK.
Abbreviationsanddefinitions
EDK
EmbeddedDevelopmentKit
Introduction
TheMicroblazeisthesoftprocessorcoreofXilinxFPGA.ItcanbeusedtotakeplaceofsomeCPUapplicationsifthesystemneedsaprocessorwhichisnotsopowerful.
ThisdocumentdescribeshowtouseMicroblazetoconfigureFPGAlocalregisters,whichcanbeusedasIPwhendebuggingFPGAwithoutacoreboard.
Functionaldescription
1.1Interface
Figure1TopLevelInterfaceofMicroblazeConfigurationBlock
PINName
I/O
Function
sys_clk_pin
I
ThesystemclockforMicroblaze.
sys_rst_pin
Systemreset,activelowforMicroblaze.
fpga_0_RS232_Uart_1_RX_pin
RXpinfromRS232UART.
fpga_0_RS232_Uart_1_TX_pin
O
TXpinfromRS232UART.
cmd_out_ch0_pin(0:
1)
CommandoutputfromMicroblaze.
Bit(0):
cs,activelow.
Bit
(1):
rw,rw=‘1’,readoperation,rw=‘0’,writeoperation.
cmd_in_ch1_pin(0:
CommandinputtoMicroblaze
ta,Whenta=‘1’,de-assertcs.
notused.
address_pin(0:
31)
RegisteraddresstoaccessFPGAregisters.
dw_ch0_pin(0:
WritedatatoFPGAregisters.
dr_ch1_pin(0:
ReaddatafromFPGAregisters.
Table1InterfaceofMicroblazeBlock
1.2AccessFPGAregisters
MicroblazeblockusedtoaccessFPGAregisterthroughUART.TheremustbeaUARTportonthePCBinordertoaccessFPGA.ThelocalinterfacewillsimulateauPinterface.
Bydefault,theUARTbaudrateis9600.ItcanbemodifiedbychangetheparametersofMicroblazesystem.
●WriteOperation
Writeoperationislaunchedbytype“setreg”commandinaHyperTerminalwindow;
otherkindofUARTTerminalcanalsobeused.
Commandsyntax:
setregaddressdata
Address&
Datacanbedecimalorhex.Ifhextypeofaddressordataisneeded,theprefix“0x”mustbeincluded.
Figure2isthewaveformofinternalinterfaceusedtoaccessFPGAregisters.
1.Aftertype“setreg”command,cswillsetto‘0’andrwwillsetto‘0’forwriteoperation.Atthesametime,registeraddressandregisterdatawillputoncorrespondingbus.
2.FPGAregistermoduleneedtoasserttasignalwhenitsuccessfullywritetherelevantregisters.
3.Then,cswillde-assert(setto‘1’),rwwillsetto‘1’(readoperationmode).
4.FPGAregistermodulede-asserttawhencsis‘1’.
WriteOperation
●ReadOperation
Readoperationislaunchedbytype“getreg”commandinaHyperTerminalwindow;
getregaddress
Addresscanbedecimalorhex.Ifhextypeofaddressisneeded,theprefix“0x”mustbeincluded.
Figure3isthewaveformofinternalinterfaceusedtoaccessFPGAregisters.
1.Aftertype“getreg”command,cswillsetto‘0’andrwwillsetto‘1’forreadoperation.Atthesametime,registeraddresswillputoncorrespondinginterface.
2.FPGAregistermoduleneedtoasserttasignalwhenitsuccessfullywritetherelevantregisters.Andputthecorrectreaddataondatabus.
3.Readdatawillbeextractedbysoftware.
4.Then,cswillde-assert(setto‘1’),rwwillsetto‘1’(readoperationmode).
5.FPGAregistermodulede-asserttawhencsis‘1’.
ReadOperation
1.3Example
Figure4ExampleofUsingMicroblaze
Figure4isaexampleofusingMicroblazeinadesign.
NOTE:
1.It’srecommendthattheMicroblazeshouldbeinstantiateonthetoplevelandthelabelnameshouldbe“system_i”.
2.AddtheattributesothatthesynthesistoolswillnotflatthehierarchyofMicroblaze.
attributeHIERARCHY:
string;
attributeHIERARCHYofsystem_i:
labelis"
preserve"
;
●system
TheMicroblazemodule,itshouldbeinstantiatewiththelabel“system_i”.Itlocatedin$EDK_PRJ\hdl.CopyittotheHDSproject.
●Int_adapt
TheadapterusedtoconnecttheMicroblazeinterfacewithlocalinterface.
●Gpio_reg
FPGAinternalregisterblock.
Theregisterblockcanbeextendedtomoreregisterblockbycascadethe‘cs’,‘rw’,‘addr’,‘dw’,‘dr’and‘ta’signals.
AfterbuildthetoplevelofFPGAdesign,youcansynthesisittogenerateedffile.Thenusethisedffileandelf(executablelinkedfile)torunPARtogeneratebitfile.Theelffilealreadygenerated,soyoujustneedtogeneratebitfileusingelffile.
Belowisthescriptofhowtogeneratebitfile.Itcanbemodifiedaccordingtothedesign.
ngdbuild-pxc5vlx50t-ff1136-1-dd./user/temp-sd./user/macro-uc./user/system.ucf-bm./user/macro/system_stub.bmm./user/macro/example_top.edf./user/par/example_top_ngdbuild.ngd
map-intstyleise-olhigh-cmspeed-ignore_keep_hierarchy-c100-txon-w-o./user/par/example_top_map.ncd./user/par/example_top_ngdbuild.ngd./user/par/example_top_map.pcf
par-w-intstyleise-olhigh-plhigh-rlhigh./user/par/example_top_map.ncd./user/par/example_top_par.ncd./user/par/example_top_map.pcf
bitgen-w-gunusedpin:
pullnone-bd./user/macro/uart_up.elf./user/par/example_top_par.ncd./user/par/example_top.bit./user/par/example_top_map.pcf
“system_stub.bmm”fileistheBlockMemoryMapfile.Itlocatedin$EDK_PRJ\implementation.CopyittowhereyouwanttorunPAR.
“uart_up.elf”istheExecutableandLinkableFormatfile.Itlocatedin$EDK_PRJ\SDK_projects\uart_up\Debug.CopyittowhereyouwanttorunPAR.
ThenetlistfilesofMicroblazesystemarelocatedin$EDK_PRJ\implementationwiththesuffix“ngc”.CopythesefiletowhereyouwanttorunPAR.
Formoreinformation,pleaseseetheexampleproject.
ModifySystemParameters
ThisexampleprojectisbasedonVirtex-5FPGA.IfothertypeofFPGAisneeded,mustmodifytheprojectoption.Itisdescribedbelow:
1.OpentheMicroblazeproject.
2.Fromtheprojectmenu,select“projectOptions…”.Thenyoucanmodifythetargetdevice.
3.IfyouwanttomodifythebaudrateofUART,youcanrightclick“RS232_Uart_1”andselect“ConfigureIP…”.Thenyoucanmodifythebaudrate.
4.Aftermodifysystemparameters,youneedtorungeneratenetlistinordertogenerate“ngc”fileofMicroblazesystem.
5.Nowyoucanregeneratebitfileasdescribedbefore.
ENDOFDOCUMENT
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