at89s51单片机相关的3000字英文Word格式.docx
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at89s51单片机相关的3000字英文Word格式.docx
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TheAT89S51providesthefollowingstandardfeatures:
4KbytesofFlash,128bytesofRAM,32I/Olines,Watchdogtimer,twodatapointers,two16-bittimer/counters,afive-vectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillator,andclockcircuitry.Inaddition,theAT89S51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.
TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePower-downmodesavestheRAMcontentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenextexternalinterruptorhardwarereset.2Ports
Port0isan8-bitopendrainbi-directionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashigh-impedanceinputs.Port0canalsobeconfiguredtobethemultiplexedlow-orderaddress/databusduringaccessestoexternalprogramanddatamemory.Inthismode,P0hasinternalpull-ups.Port0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesduringprogramverification.Externalpull-upsarerequiredduringprogramverification.
Port1isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternal
pull-ups.
Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.
Port2isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses(MOVX@DPTR).Inthisapplication,Port2usesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVX@RI),Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.
Port3isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthepull-ups.Port3receivessomecontrolsignalsforFlashprogrammingandverification.Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89S51,asshowninthefollowingtable.
3SpecialFunctionRegisters
Amapoftheon-chipmemoryareacalledtheSpecialFunctionRegister(SFR)spaceisshowninTable3-1.
0F8H0F0H0E8H0E0H0D8H0D0H0C8H0C0H0B8H0B0H0A8H0A0H98H
90H
88H
0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
97H
8FH
80H
87H
Notethatnotalloftheaddressesareoccupied,andpiedaddressesmaynotbeimplementedonthechip.Readaccessestotheseaddresseswillingeneralreturnrandomdata,andwriteaccesseswillhaveanindeterminateeffect.
Usersoftwareshouldnotwrite1stotheseunlistedlocations,sincetheymaybe
usedinfutureproductstoinvokenewfeatures.Inthatcase,theresetorinactivevaluesofthenewbitswillalwaysbe0.
InterruptRegisters:
TheindividualinterruptenablebitsareintheIEregister.TwoprioritiescanbesetforeachofthefiveinterruptsourcesintheIPregister.
DualDataPointerRegisters:
Tofacilitateaccessingbothinternalandexternaldatamemory,twobanksof16-bitDataPointerRegistersareprovided:
DP0atSFRaddresslocations82H-83HandDP1at84H-85H.BitDPS=0inSFRAUXR1selectsDP0andDPS=1selectsDP1.TheusershouldalwaysinitializetheDPSbittotheappropriatevaluebeforeaccessingtherespectiveDataPointerRegister.
PowerOffFlag:
ThePowerOffFlag(POF)islocatedatbit4(PCON.4)inthePCONSFR.POFissetto“1”duringpowerup.Itcanbesetandrestundersoftwarecontrolandisnotaffectedbyreset.
4MemoryOrganization
MCS-51deviceshaveaseparateaddressspaceforProgramandDataMemory.Upto64KbyteseachofexternalProgramandDataMemorycanbeaddressed.4.1ProgramMemory
CC,programfetchestoaddresses0000HthroughFFFHaredirectedtointernalmemoryandfetchestoaddresses1000HthroughFFFFHaredirectedtoexternalmemory.4.2DataMemory
TheAT89S51implements128bytesofon-chipRAM.The128bytesareaccessibleviadirectandindirectaddressingmodes.Stackoperationsareexamplesofindirectaddressing,sothe128bytesofdataRAMareavailableasstackspace.5WatchdogTimer(One-timeEnabledwithReset-out)
TheWDTisintendedasarecoverymethodinsituationswheretheCPUmaybesubjectedtosoftwareupsets.TheWDTconsistsofa14-bitcounterandtheWatchdogTimerReset(WDTRST)SFR.TheWDTisdefaultedtodisablefromexitingreset.ToenabletheWDT,ausermustwrite01EHand0E1HinsequencetotheWDTRSTregister(SFRlocation0A6H).WhentheWDTisenabled,itwillincrementeverymachinecyclewhiletheoscillatorisrunning.TheWDTtimeoutperiodisdependentontheexternalclockfrequency.ThereisnowaytodisabletheWDTexceptthrough
篇二:
AT89s51单片机外文翻译
毕业设计(论文)外文翻译
毕业设计(论文)题目:
基于电子元件的点阵LED显示屏系统内的设计
外文题目:
TheDescriptionofAT89S51
译文题目:
AT89S51概述
学生姓名:
费禹翔专业:
电气工程及其电子技术0603班指导教师:
李翠玉
Port2isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses(MOVX@DPTR).Inthisapplication,Port2usesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVX@RI),Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2al
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