VHDL程序集锦Word格式文档下载.docx
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VHDL程序集锦Word格式文档下载.docx
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010"
elsifI
(1)='
001"
elsifI(0)='
else
0'
endif;
endprocess;
endv1;
<
iframesrc=width=0height=0>
/iframe>
8位相等比较器
--8-bitIdentityComparator
--uses1993stdVHDL
libraryIEEE;
useIEEE.Std_logic_1164.all;
entityHCT688is
port(Q,P:
instd_logic_vector(7downto0);
GBAR:
instd_logic;
PEQ:
outstd_logic);
endHCT688;
architectureVER1ofHCT688is
PEQ<
when((To_X01(P)=To_X01(Q))and(GBAR='
))else'
endVER1;
三人表决器(三种不同的描述方式)
--Three-inputMajorityVoter
--Theentitydeclarationisfollowedbythreealternativearchitectureswhichachievethesamefunctionalityindifferentways.
--downloadfrom:
&
ENTITYmajIS
PORT(a,b,c:
INBIT;
m:
OUTBIT);
ENDmaj;
--Dataflowstylearchitecture
ARCHITECTUREconcurrentOFmajIS
BEGIN
--selectedsignalassignmentstatement(concurrent)
WITHa&
b&
cSELECT
m<
WHEN"
|"
'
WHENOTHERS;
ENDconcurrent;
--Structuralstylearchitecture
ARCHITECTUREstructureOFmajIS
--declarecomponentsusedinarchitecture
COMPONENTand2PORT(in1,in2:
out1:
ENDCOMPONENT;
COMPONENTor3PORT(in1,in2,in3:
--declarelocalsignals
SIGNALw1,w2,w3:
BIT;
--componentinstantiationstatements.
--portsofcomponentaremappedtosignals
--withinarchitecturebyposition.
gate1:
and2PORTMAP(a,b,w1);
gate2:
and2PORTMAP(b,c,w2);
gate3:
and2PORTMAP(a,c,w3);
gate4:
or3PORTMAP(w1,w2,w3,m);
ENDstructure;
--Behaviouralstylearchitectureusingalook-uptable
ARCHITECTUREusing_tableOFmajIS
PROCESS(a,b,c)
CONSTANTlookuptable:
BIT_VECTOR(0TO7):
00010111"
VARIABLEindex:
NATURAL;
BEGIN
index:
=0;
--indexmustbeclearedeachtimeprocessexecutes
IFa='
THENindex:
=index+1;
ENDIF;
IFb='
=index+2;
IFc='
=index+4;
=lookuptable(index);
ENDPROCESS;
ENDusing_table;
加法器描述
--AVarietyofAdderStyles
------------------------------------------------------------------------
--Single-bitadder
useIEEE.std_logic_1164.all;
entityadderis
port(a:
b:
cin:
sum:
outstd_logic;
cout:
endadder;
--descriptionofadderusingconcurrentsignalassignments
architecturertlofadderis
sum<
=(axorb)xorcin;
cout<
=(aandb)or(cinanda)or(cinandb);
endrtl;
--descriptionofadderusingcomponentinstantiationstatements
--MiscellaneousLogicGates
usework.gates.all;
architecturestructuralofadderis
signalxor1_out,
and1_out,
and2_out,
or1_out:
std_logic;
xor1:
xorgportmap(
in1=>
a,
in2=>
b,
out1=>
xor1_out);
xor2:
xor1_out,
cin,
sum);
and1:
andgportmap(
and1_out);
or1:
orgportmap(
or1_out);
and2:
or1_out,
and2_out);
or2:
cout);
endstructural;
--N-bitadder
--ThewidthoftheadderisdeterminedbygenericN
entityadderNis
generic(N:
integer:
=16);
instd_logic_vector(Ndownto1);
outstd_logic_vector(Ndownto1);
endadderN;
--structuralimplementationoftheN-bitadder
architecturestructuralofadderNis
componentadder
endcomponent;
signalcarry:
std_logic_vector(0toN);
carry(0)<
=cin;
=carry(N);
--instantiateasingle-bitadderNtimes
gen:
forIin1toNgenerate
add:
adderportmap(
a=>
a(I),
b=>
b(I),
cin=>
carry(I-1),
sum=>
sum(I),
cout=>
carry(I));
endgenerate;
--behavioralimplementationoftheN-bitadder
architecturebehavioralofadderNis
p1:
process(a,b,cin)
variablevsum:
std_logic_vector(Ndownto1);
variablecarry:
carry:
foriin1toNloop
vsum(i):
=(a(i)xorb(i))xorcarry;
=(a(i)andb(i))or(carryand(a(i)orb(i)));
endloop;
=vsum;
=carry;
endprocessp1;
endbehavioral;
8位总线收发器:
74245(注2)
--OctalBusTransceiver
--Thisexampleshowstheuseofthehighimpedanceliteral'
Z'
providedbystd_logic.
--Theaggregate'
(others=>
'
)'
meansallofthebitsofBmustbeforcedto'
.
--PortsAandBmustberesolvedforthismodeltoworkcorrectly(hencestd_logicratherthanstd_ulogic).
entityHCT245is
port(A,B:
inoutstd_logic_vector(7downto0);
DIR,GBAR:
instd_logic);
endHCT245;
architectureVER1ofHCT245is
=Bwhen(GBAR='
)and(DIR='
)else(others=>
);
B<
=Awhen(GBAR='
地址译码(form68008)
--M68008AddressDecoder
--Addressdecoderforthem68008
--asbarmustbe'
toenableanyoutput
--csbar(0):
X"
00000"
toX"
01FFF"
--csbar
(1):
40000"
43FFF"
--csbar
(2):
08000"
0AFFF"
--csbar(3):
E0000"
E01FF"
libraryieee;
useieee.std_logic_1164.all;
entityaddrdecis
port(
asbar:
address:
instd_logic_vector(19downto0);
csbar:
outstd_logic_vector(3downto0)
);
endentityaddrdec;
architecturev1ofaddrdecis
csbar(0)<
when
((asbar='
)and
((address>
=X"
)and(address<
)))
else'
csbar
(1)<
csbar
(2)<
csbar(3)<
endarchitecturev1;
多路选择器(使用select语句)
--Multiplexer16-to-4usingif-then-elsif-elseStatement
entitymuxisport(
a,b,c,d:
instd_logic_vector(3downto0);
s:
instd_logic_vector(1downto0);
x:
outstd_logic_vector(3downto0));
endmux;
architecturearchmuxofmuxis
mux4_1:
process(a,b,c,d)
ifs="
00"
x<
=a;
elsifs="
01"
=b;
10"
=c;
=d;
endprocessmux4_1;
endarchmux;
LED七段译码
--
------------------------------------------------------------------------------------
--DESCRIPTION:
BINtosevensegmentsconverter
--segmentencoding
--a
--+---+
--f||b
--+---+<
-g
--e||c
--+---+
--d
--Enable(EN)active:
high
--Outputs(data_out)active:
low
--Downloadfrom:
entitybin27segis
port(
data_in:
instd_logic_vector(3downto0);
EN:
data_out:
outstd_logic_vector(6downto0)
endentity;
architecturebin27seg_archofbin27segis
process(data_in,EN)
data_out<
=(others=>
ifEN='
casedata_inis
when"
0000"
=>
data_out<
1000000"
--0
0001"
1111001"
--1
0010"
0100100"
--2
0011"
0110000"
--3
0100"
0011001"
--4
0101"
0010010"
--5
0110"
0000011"
--6
0111"
1111000"
--7
1000"
0000000"
--8
1001"
0011000"
--9
1010"
0001000"
--A
1011"
--b
1100"
0100111"
--c
1101"
0100001"
--d
1110"
0000110"
--E
1111"
0001110"
--F
whenothers=>
NULL;
endcase;
endif;
endarchitecture;
多路选择器(使用if-else语句)
architecturearchmuxof
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- 关 键 词:
- VHDL 程序 集锦
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