Based on SCM multifunctional temperature testing system designWord格式文档下载.docx
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Based on SCM multifunctional temperature testing system designWord格式文档下载.docx
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(1)AT89C51SCMareintroduced
TheAT89C51isalow-power,high-performanceCMOS8-bitmicrocomputerwith4KbytesofFlashprogrammableanderasablereadonlymemory(PEROM)and128bytesofdatarandom-accessmemory(RAM).ThedeviceismanufacturedusingATMELCo.’shigh-densitynonvolatilememorytechnologyandiscompatiblewiththeindustry-standardMCS-51instructionsetandpin-out.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememoryprogrammer.Bycombiningaversatile8-bitCPUwithFlashonamonolithicchip,theATMELCo.’sAT89C51isapowerfulmicrocomputerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.
Features:
·
CompatiblewithinstructionsetofMCS-51products
4Kbytesofin-systemreprogrammableFlashmemory
Endurance:
1000write/erasecycles
Fullystaticoperation:
0Hzto24MHz
Three-levelprogrammemorylock
128×
8-bitinternalRAM
32programmableI/Olines
Two16-bitTimer/Counters
Sixinterruptsource
Programmableserialchannel
Low-poweridleandPower-downmodes
FunctionCharacteristicDescription:
TheAT89C51providesthefollowingstandardfeatures:
4KbytesofFlashmemory,128bytesofRAM,32I/Olines,two16-bittimer/counters,afivevectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillatorandclockcircuitry.Inaddition,theAT89C51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialportandinterruptsystemtocontinuefunctioning.ThePower-downModesavestheRAMcontentsbutfreezestheoscillatordisablingallotherchipfunctionsuntilthenexthardwarereset.
PinDescription:
VCC:
Supplyvoltage
GND:
Ground
Port0:
Port0isan8-bitopen-drainbi-directionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashighimpedanceinputs.
Port0mayalsobeconfiguredtobethemultiplexedloworderaddress/busduringaccessestoexternalprogramanddatamemory.InthismodeP0hasinternalpullups.
Port0alsoreceivesthecodebytesduringFlashprogramming,andoutputsthecodebytesduringprogramverification.Externalpullupsarerequiredduringprogramverification.
Port1:
Port1isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.
Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.
Port2:
Port2isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.
Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorywhichuses16-bitaddresses(MOVX@DPTR).Inthisapplication,itusesstronginternalpullupswhenemitting1s.Duringaccessestoexternaldatamemorywhichuses8-bitaddresses(MOVX@RI).Port2emitsthecontentsoftheP2SpecialFunctionRegister.
Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.
Port3:
Port3isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthepullups.
Port3alsoreceivessomecontrolsignalsforFlashprogrammingandverification.
RST:
Resetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.
ALE/
:
AddressLatchEnableoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput(
)duringFlashprogramming.InnormaloperationALEisemittedataconstantrateof1/6theoscillatorfrequency,andmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskippedduringeachaccesstoexternalDataMemory.
Ifdesired,ALEoperationcanbedisabledbysettingbit0ofSFRlocation8EH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledhigh.SettingtheALE-disablebithasnoeffectifthemicrocontrollerisinexternalexecutionmode.
:
ProgramStoreEnableisthereadstrobetoexternalprogrammemory.WhentheAT89C51isexecutingcodefromexternalprogrammemory,
isactivatedtwiceeachmachinecycle,exceptthattwo
activationsareskippedduringeachaccesstoexternaldatamemory.
EA/VPP:
ExternalAccessEnable.EAmustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFH.Note,however,thatiflockbit1isprogrammed,EAwillbeinternallylatchedonreset.EAshouldbestrappedtoVCCforinternalprogramexecutions.
Thispinalsoreceivesthe12-voltprogrammingenablevoltage(VPP)duringFlashprogramming,forpartsthatrequire12-voltVPP.
XTAL1:
Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit.
XTAL2:
Outputfromtheinvertingoscillatoramplifier.
Ready/
TheprogressofbyteprogrammingcanalsobemonitoredbytheRDY/
outputsignal.P3.4ispulledlowafterALEgoeshighduringprogrammingtoindicateBUSY.P3.4ispulledhighagainwhenprogrammingisdonetoindicateREADY.
OscillatorCharacteristics:
XTAL1andXTAL2aretheinputandoutput,respectively,ofaninvertingamplifierwhichcanbeconfiguredforuseasanon-chiposcillator.Eitheraquartzcrystalorceramicresonatormaybeused.
Todrivethedevicefromanexternalclocksource,XTAL2shouldbeleftunconnectedwhileXTAL1isdriven.
Therearenorequirementsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclockingcircuitryisthroughadividebytwofliptrigger,butminimumandmaximumvoltagehighandlowtimespecificationsmustbeobserved.
IdleMode:
Inidlemode,theCPUputsitselftosleepwhilealltheon-chipperipheralsremainactive.Themodeisinvokedbysoftware.Thecontentoftheon-chipRAMandallthespecialfunctionsregistersremainunchangedduringthismode.Theidlemodecanbeterminatedbyanyenabledinterruptorbyahardwarereset.
Itshouldbenotedthatwhenidleisterminatedbyahardwarereset,thedevicenormallyresumesprogramexecution,fromwhereitleftoff,uptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrol.On-chiphardwareinhibitsaccesstointernalRAMinthisevent,butaccesstotheportpinsisnotinhibited.ToeliminatethepossibilityofanunexpectedwritetoaportpinwhenIdleisterminatedbyreset,theinstructionfollowingtheonethatinvokesIdleshouldnotbeonethatwritestoaportpinortoexternalmemory.
Power-downMode:
Inthepower-downmode,theoscillatorisstopped,andtheinstructionthatinvokespower-downisthelastinstructionexecuted.Theon-chipRAMandspecialfunctionregistersretaintheirvaluesuntilthepower-downmodeisterminated.Theonlyexitfrompower-downisahardwarereset.Resetredefinesthespecialfunctionregistersbutdoesnotchangetheon-chipRAM.TheresetshouldnotbeactivatedbeforeVCCisrestoredtoitsnormaloperatinglevelandmustbeheldactivelongenoughtoallowtheoscillatortorestartandstabilize.
ProgramMemoryLockBits:
Whenlockbit1isprogrammed,thelogiclevelattheEApinissampledandlatchedduringreset.Ifthedeviceispoweredupwithoutareset,thelatchinitializestoarandomvalue,andholdsthatvalueuntilresetisactivated.ItisnecessarythatthelatchedvalueofEAbeinagreementwiththecurrentlogiclevelatthatpininorderforthedevicetofunctionproperly.
ProgrammingtheFla
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