EDA刘艳萍第4章习题答案Word文件下载.docx
- 文档编号:16443639
- 上传时间:2022-11-23
- 格式:DOCX
- 页数:31
- 大小:147.73KB
EDA刘艳萍第4章习题答案Word文件下载.docx
《EDA刘艳萍第4章习题答案Word文件下载.docx》由会员分享,可在线阅读,更多相关《EDA刘艳萍第4章习题答案Word文件下载.docx(31页珍藏版)》请在冰豆网上搜索。
ifcnt=max_valuethen
cnt<
else
=cnt+1;
endif;
else
ifcnt=0then
=max_value;
=cnt-1;
endif;
ENDPROCESS;
count<
=cnt;
Co<
=‘1’when(cnt=max_valueanddir=‘1’)or(cnt=0anddir=‘0’)else
‘0’;
Enda;
(2)计数结果由共阴极七段数码管显示
outstd_logic_vector(0to6);
ifclr=’0’thencnt<
withcntselect
count<
=“0000110"
when1,--1
“1011011"
when2,--2
“1001111"
when3,--3
“1100110"
when4,--4
“1101101"
when5,--5
“1111101"
when6,--6
“0000111"
when7,--7
“1111111"
when8,--8
“1101111"
when9,--9
:
“1110001”when15,--F
“0111111"
whenothers;
(3)结果显示为十进制数
(clk,clk1,clr,en,load,dir:
Scanout:
outstd_logic_vector(0to1);
co:
signalcnt1:
integerrange0to9;
signalcnt2:
integerrange0to1;
signalhex:
signalscan:
std_logic_vector(0to1);
ifclr=‘0’thencnt<
PROCESS(clk1)
IF(clk1'
EVENTANDclk1='
ifscan=“00”orscan>
=“10”thenscan<
=“01”;
elsescan<
=scan+’1’;
endIF;
Scanout<
=scan;
Cnt1<
=cntwhencnt<
=9elsecnt-10;
Cnt2<
=1whencnt>
=10else0;
Hex<
=cnt2whenscan=”01”elseCnt1;
withhexselect
4-5:
libraryieee;
useieee.std_logic_1164.all;
entitycl5is
port(clk:
dir:
instd_logic;
d:
q:
outstd_logic);
endcl5;
architectureaofcl5is
signalreg:
std_logic_vector(0to3);
begin
process(clk)
ifclk'
eventandclk='
ifdir='
reg<
=reg(1to3)&
d;
else
=d&
reg(0to2);
ifdir='
q<
=reg(0);
else
=reg(3);
endprocess;
enda;
4-8:
libraryIEEE;
useIEEE.Std_logic_1164.all;
useIEEE.STD_LOGIC_UNSIGNED.a11;
entitycounteris
port(CLK,m0,m1:
inSTD_LOGIC;
Y0:
outSTD_LOGIC_VECTOR(0to4));
Endcounter;
Architecturertlofcounteris
SignalCNT:
STD_LOGIC_VECTOR(0to4);
process(CLK)
begin
ifCLK'
eventandCLK=’1’then
if(M1=’0’ANDM0=’0’)THEN
Ifcnt>
=”10011”then
CNT<
=”00000”;
else
CNT<
=CNT+’1’;
Endif;
ELSif(M1=’0’ANDM0=’1’)THEN
=”00100”then
ELSif(M1=’1’ANDM0=’0’)THEN
=”01010”then
Endif;
=”00110”then
Endif;
Endif;
ENDIF;
Endprocess;
Y0<
=cnt;
endrtl;
4-9:
entityseq_genis
port(CIK:
outSTD_LOGIC_VECTOR(0to9));
Endseq_gen;
Architecturertlofseq_genis
STD_LOGIC_VECTOR(3downto0);
Ifcnt=”1001”then
=”0000”;
Endif;
WithCNTSelect
=“1000000000”when“0000”,
“0100000000”when“0001”,
“0010000000”when“0010”,
“0001000000”when“0011”,
“0000100000”when“0100”,
“0000010000”when“0101”,
“0000001000”when“0110”,
“0000000100”when“0111”,
“0000000010”when“1000”,
“0000000001”whenothers;
endrtl;
或者:
entityclis
outstd_logic_vector(9downto0));
endcl;
architectureaofclis
variablei:
integerrange0to9;
variableb:
std_logic_vector(9downto0);
b:
="
0000000000"
;
ifi=9then
i:
=0;
b:
0000000001"
=i+1;
b(i):
='
q<
=b;
entitycl7is
endcl7;
architectureaofcl7is
=b(8downto0)&
'
0'
4-10:
(a)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYdff2IS
PORT(s,a,b:
INSTD_LOGIC;
out1:
bufferSTD_LOGIC);
ENDdff2;
ARCHITECTURErtlOFdff2IS
Signalz,d:
std_logic;
PROCESS(a,b,s)
BEGIN
If(s=‘0’)thenz<
a;
Elsez<
ENDPROCESS;
d<
=out1;
PROCESS(z)
IF(z‘EVENTANDz=‘1’)THEN
Out1<
=d;
ENDIF;
ENDrtl;
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
PORT(s,a,b:
iNSTD_LOGIC;
out1:
bufferSTD_LOGIC);
ENDdff2;
PROCESS(a,b,s,z)
If(s='
)thenz<
=a;
Elsez<
D<
IF(z'
EVENTANDz='
)THEN
=d;
ENDIF;
ENDPROCESS;
d<
ENDrtl;
(b)
PORT(s,a,b,clk:
out2:
OUTSTD_LOGIC);
Signalz:
PROCESS(clk)
IF(clk‘EVENTANDclk=‘1’)THEN
Out2<
=z;
(c)
PORT(s,d,a,b:
Out3:
PROCESS(z)
Out3<
=D;
4-11:
一位半减器
entityh_subis
port(x,y:
inbit;
diff,sub_out:
outbit);
endH_sub;
architecturefuncofh_subis
process(x,y)
variablecon:
bit_vector(1downto0);
variablecom:
com:
=x&
y;
if(com=“00”)thencon:
=“00”;
elsif(com=“01”)thencon:
=“11”;
elsif(com=“10”)thencon:
=“01”;
elsif(com=“11”)thencon:
diff<
=con
(1);
sub_out<
=con(0);
endfunc;
一位全减器描述:
结构描述方法
useIEEE.STD_LOGIC_1164.all;
entityfull_subis
port(x,y,sub_in:
endfull_sub;
architecturertloffull_subis
componentH_subis
port(x,y:
endcomponent;
signaldiff1,sub_out1,sub_out2:
bit;
u1:
H_subportmap(x,y,diff1,sub_out1(0));
u2:
H_subportmap(diff1,sub_in,diff,sub_out2);
sub_out<
=sub_out1orsub_out2;
endrtl;
(2)一位全减器描述:
entityall_subis
port(x,y,sub_in:
architecturefuncofall_subis
process(x,y,sub_in)
variablecon:
bit_vector(2downto0);
y&
sub_in;
if(com=“000”)thencon:
elsif(com=“011”)thencon:
elsif(com=“100”)thencon:
=“10”;
elsif(com=“101”)thencon:
elsif(com=“110”)thencon:
elsecon:
8位减法器描述:
entitysubtracteris
port(a,b:
inbit_vector(7dowto0);
sub_in:
diff:
outbit_vector(7dowto0);
sub_out:
endsubtracter;
architecturestruofsubtracteris
componentall_sub
signalsub:
bit_vector(8downto0);
g0:
forIin0to7generate
u_inst:
all_subbportmap(a(i),b(i),sub(i),diff(i),sub(i+1));
endgenerate;
sub(0)<
=su
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- EDA 刘艳萍第 习题 答案