计算机体系结构课后习题文档格式.docx
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计算机体系结构课后习题文档格式.docx
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答:
(1)Assume:
thefractionofthetimeenhancement3mustbeusedtoachieveanoverallspeedupof10isx.
So,x=45%
(2)Assume:
ThetotalexecutiontimebeforethethreeenhancementscanbeusedisTimebefore,TheexecutiontimefornoenhancementisTimeno.
ThetotalexecutiontimeafterthethreeenhancementscanbeusedisTimeafter
So,
(3)By
Ifonlyoneenhancementcanbeimplemented:
So,wemustselectenhancement1and3tomaximizeperformance.
1.2Supposethereisagraphicsoperationthataccountsfor10%ofexecutiontimeinanapplication,andbyaddingspecialhardwarewecanspeedthisupbyafactorof18.Infurther,wecouldusetwiceasmuchhardware,andmakethegraphicsoperationrun36timesfaster.Givethereasonofwhetheritisworthexploringsuchanfurtherarchitecturalchange?
So,Itisnotworthexploringsuchanfurtherarchitecturalchange.
1.3Inmanypracticalapplicationsthatdemandareal-timeresponse,thecomputationalworkloadWisoftenfixed.Asthenumberofprocessorsincreasesinaparallelcomputer,thefixedworkloadisdistributedtomoreprocessorsforparallelexecution.Assume20percentofWmustbeexecutedsequentially,and80percentcanbeexecutedby4nodessimultaneously.Whatisafixed-loadspeedup?
So,afixed-loadspeedupis2.5.
2.1Thereisamodelmachinewithnineinstructions,whichfrequenciesareADD(0.3),SUB(0.24),JOM(0.06),STO(0.07),JMP(0.07),SHR(0.02),CIL(0.03),CLA(0.2),STP(0.01),respectively.ThereareseveralGPRsinthemachine.Memoryisbyteaddressable,withaccessedaddressesaligned.Andthememorywordwidthis16bit.
Supposethenineinstructionswiththecharacteristicsasfollowing:
nTwooperandsinstructions
nTwokindsofinstructionlength
nExtendedcoding
nShorterinstructionoperandsformat:
R(register)-R(register)
nLongerinstructionoperandsformat:
R(register)-M(memory)
nWithdisplacementmemoryaddressingmode
A.EncodethenineinstructionswithHuffman-coding,andgivetheaveragecodelength.
B.Designedthepracticalinstructioncodes,andgivetheaveragecodelength.
C.Writethetwoinstructionwordformatsindetail.
D.Whatisthemaximumoffsetforaccessingmemoryaddress?
HuffmancodingbyHuffmantree
nADD30%01
nSUB24%11
nCLA20%10
nJOM6%0001
nSTO7%0011
nJMP7%0010
nSHR2%000001
nCIL3%00001
nSTP1%000000
So,theaveragecodelengthis
(B)Twokindsofinstructionlengthextendedcoding
nSUB24%11
nCLA20%10
nJOM6%11000
nSTO7%11001
nJMP7%11010
nSHR2%11011
nCIL3%11100
nSTP1%11101
(C)Shorterinstructionformat:
Opcode
2bits
Register
3bits
Longerinstructionformat:
opcode
5bits
offset
(D)Themaximumoffsetforaccessingmemoryaddressis32bytes.
3.1Identifyallofthedatadependencesinthefollowingcode.Whichdependencesaredatahazardsthatwillberesolvedviaforwarding?
ADDR2,R5,R4
ADDR4,R2,R5
SWR5,100(R2)
ADDR3,R2,R4
3.2Howcouldwemodifythefollowingcodetomakeuseofadelayedbranchslot?
Loop:
LWR2,100(R3)
ADDIR3,R3,#4
BEQR3,R4,Loop
LWR2,100(R3)
Loop:
ADDIR3,R3,#4
BEQR3,R4,Loop
DelayedbranchslotLWR2,100(R3)
3.3Considerthefollowingreservationtableforafour-stagepipelinewithaclockcyclet=20ns.
A.Whataretheforbiddenlatenciesandtheinitialcollisionvector?
B.Drawthestatetransitiondiagramforschedulingthepipeline.
C.DeterminetheMALassociatedwiththeshortestgreedycycle.
D.DeterminethepipelinemaximumthroughputcorrespondingtotheMALandgivent.
s1
s2
s3
s4
123456
×
A.theforbiddenlatenciesF={1,2,5}
theinitialcollisionvectorC=(10011)
B.thestatetransitiondiagram
C.MAL(MinimalAverageLatency)=3clockcycles
D.ThepipelinemaximumthroughputHk=1/(3×
20ns)
3.4Usingt
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