基于单片机的智能晾衣架控制系统的设计与实现外文文献原稿和译文Word格式.docx
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基于单片机的智能晾衣架控制系统的设计与实现外文文献原稿和译文Word格式.docx
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4KbytesofFlash,128bytesofRAM,32I/Olines,Watchdogtimer,twodatapointers,two16-bittimer/counters,afive-vectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillator,andclockcircuitry.Inaddition,theAT89S51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.
TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePower-downmodesavestheRAMcontentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenextexternalinterruptorhardwarereset.
2Ports
Port0isan8-bitopendrainbi-directionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashigh-impedanceinputs.Port0canalsobeconfiguredtobethemultiplexedlow-orderaddress/databusduringaccessestoexternalprogramanddatamemory.Inthismode,P0hasinternalpull-ups.Port0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesduringprogramverification.Externalpull-upsarerequiredduringprogramverification.
Port1isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups.
Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.
PortPin
AlternateFunctions
P1.5
MOSI(usedforIn-SystemProgramming)
P1.6
MOSO(usedforIn-SystemProgramming)
P1.7
SCK(usedforIn-SystemProgramming)
Port2isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses(MOVX@DPTR).Inthisapplication,Port2usesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVX@RI),Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.
Port3isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthepull-ups.Port3receivessomecontrolsignalsforFlashprogrammingandverification.Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89S51,asshowninthefollowingtable.
P3.0
RXD(serialinputport)
P3.1
TXD(serialoutputport)
P3.2
INT0(externalinterrupt0)
P3.3
INT1(externalinterrupt1)
P3.4
T0(timer0externalinput)
P3.5
T1(timer1externalinput)
P3.6
WR(externaldatamemorywritestrobe)
P3.7
RD(externaldatamemoryreadstrobe)
3SpecialFunctionRegisters
Amapoftheon-chipmemoryareacalledtheSpecialFunctionRegister(SFR)spaceisshowninTable3-1.
Table3-1.AT89S51SFRMapandResetValues
0F8H
0FFH
0F0H
B
00000000
0F7H
0E8H
0EFH
0E0H
ACC00000000
0E7H
0D8H
0DFH
0D0H
PSW00000000
0D7H
0C8H
0CFH
0C0H
0C7H
0B8H
IPXX000000
0BFH
0B0H
P311111111
0B7H
0A8H
IE0X000000
0AFH
0A0H
P211111111
AUXR1XXXXX
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