自动售货机设计VerilogWord文档格式.docx
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自动售货机设计VerilogWord文档格式.docx
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moduleauto_vending(clk,cel_cola,cel_diet,reset,coin_ten,coin_five,ok_buy,cancel_buy,//输入
led_cola_ok,led_diet_ok,led_buy,led_cancel,led_cola_out,led_diet_out,shu_cola_sel,shu_diet_sel,
led_display,shu_money_return,Hex);
//输出
inputclk,cel_cola,cel_diet,reset,coin_ten,coin_five,ok_buy,cancel_buy;
outputled_cola_ok,led_diet_ok,//表示还有存货
led_buy,led_cancel,//表示选择购买和取消购买
led_cola_out,led_diet_out;
//显示表示已出货
//led_return;
//每四秒闪烁一次代表被退之硬币
wire[10:
0]led_cola_sel,led_diet_sel;
////选中饮料的数量
output[6:
0]shu_cola_sel,shu_diet_sel;
output[13:
0]led_display;
//表示投币的金额
0]shu_money_return;
wireok,cancel,money_ok;
//在ok_or_cancel出来的
//wire[10:
0]no_diet,no_cola;
//售货机内的饮料数量
0]money_return;
//reg[10:
0]no_sock_cola,no_sock_diet;
0]total_count,total_consum;
0]Hex;
assignHex=14'
b111_111_111_11111;
parameterIdle=2'
d0,
S1=2'
d1,
S2=2'
d2;
reg[1:
0]state;
regclk_1;
regrst;
reg[29:
0]count;
always@(posedgeclk)//shengcheng1sdeshizhong
begin
if(count==30'
d)
begin
clk_1<
=~clk_1;
count<
=0;
end
else
=count+1;
end
always@(posedgeclk_1ornegedgereset)
if(!
reset)
begin
state<
=Idle;
rst<
end
case(state)
Idle:
rst<
state<
=S1;
end
S1:
=1;
if(ok_buy||cancel_buy)
endcase
wirebuyok;
toubiu1(rst,clk,coin_five,coin_ten,led_display,total_count);
select_drinku2(clk,rst,cel_cola,cel_diet,/*no_cola,no_diet,*/
led_cola_sel,led_diet_sel,/*led_cola_ok,led_diet_ok,*/total_consum);
ok_or_cancelu3(clk,rst,ok_buy,cancel_buy,ok,cancel,led_buy,led_cancel);
give_checku4(reset,buyok,clk,ok,money_ok,rst,led_cola_out,led_diet_out,
led_cola_sel,led_diet_sel,led_cola_ok,led_diet_ok/*no_cola,no_diet*/);
coin_returnu5(clk,rst,ok_buy,money_return,total_count,total_consum,money_ok,cancel_buy,cancel);
xianshiq1(led_cola_sel,shu_cola_sel);
xianshiq2(led_diet_sel,shu_diet_sel);
xianshi2w2(money_return,shu_money_return);
endmodule
///显示数量的
modulexianshi(a,b);
//用来显示
input[10:
0]a;
outputreg[6:
0]b;
always@(a)
case(a)
11'
d0:
b<
=7'
b1000000;
d1:
b1111001;
d2:
b0100100;
d3:
b0110000;
d4:
b0011001;
d5:
b0010010;
d6:
b0000010;
d7:
b1111000;
d8:
b0000000;
d9:
b0010000;
endcase
//钱数显示
modulexianshi2(total_count,led_display);
0]total_count;
outputreg[13:
always@(total_count)
case(total_count)
led_display<
=14'
b1000000_1000000;
b1000000_0010010;
b1111001_1000000;
b1111001_0010010;
b0100100_1000000;
b0100100_0010010;
b0110000_1000000;
b0110000_0010010;
b0011001_1000000;
11'
b0011001_0010010;
d10:
b0010010_1000000;
d11:
b0010010_0010010;
d12:
b0000010_1000000;
d13:
b0000010_0010010;
d14:
b1111000_1000000;
d15:
b1111000_0010010;
d16:
b0000000_1000000;
d17:
b0000000_0010010;
d18:
b0010000_1000000;
d19:
b0010000_0010010;
//去抖模块
modulequdou(clk,reset,k,key);
inputk,reset,clk;
outputregkey;
reg[10:
0]clock;
always@(posedgeclk)
if(!
clock<
=11'
d0;
else
if(k)
key<
=clock+1;
if(clock==1000)
clock<
b0;
key=0;
end
end
/////投币电路
moduletoubi(reset,clk,coin_05,coin_10,led_display,total_count);
//加一个去抖模块
inputreset,clk,coin_05,coin_10;
outputreg[10:
//统计投入里面的金币
wirequ_coin_05,qu_coin_10;
qudoua1(clk,reset,coin_05,qu_coin_05);
qudoua2(clk,reset,coin_10,qu_coin_10);
0]count_1,count_2;
always@(negedgequ_coin_05ornegedgereset)
beginif(!
count_1<
elseif(!
qu_coin_05)
begin
count_1<
=count_1+11'
d1;
end
always@(negedgequ_coin_10or
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- 自动 售货 设计 Verilog
