eda报告多功能数字钟设计Word格式.docx

eda报告多功能数字钟设计Word格式.docx

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这些模块在顶层原理图中相互连接作用2.2总体设计框图3设计原理分析3.1分频器分频模块：

将20Mhz晶振分频为1hz，100hz,1000hz分别用于计数模块，秒表模块，状态机模块moduleoclk（CLK,oclk,rst,clk_10,clk_100）;

inputCLK,rst;

outputoclk,clk_10,clk_100;

reg32:

0cnt,cnt1,cnt2;

regoclk,clk_10,clk_100;

always（posedgeCLKornegedgerst）beginif（!

rst）begincnt=0;

oclk=0;

endelseif（cnt10000-1）cnt=cnt+1;

elsebegincnt=0;

oclk=oclk;

endendalways（posedgeCLKornegedgerst）beginif（!

rst）begincnt1=0;

clk_10=0;

endelseif（cnt1=10000000-1）cnt1=cnt1+1;

elsebegincnt1=0;

clk_10=clk_10;

rst）begincnt2=0;

clk_100=0;

endelseif（cnt2100000-1）cnt2=cnt2+1;

elsebegincnt2=0;

clk_100=clk_100;

endendendmodule3.2计时器和时间调节计时模块：

检测posedgeclk_10并进行计数，同时能调时调分，最后是整点报时部分modulecni（clk_10,rst,tiaoshi,tiaofen,ge,shi,bai,qian,wan,shiwan,bee）;

inputclk_10,rst,tiaoshi,tiaofen;

outputreg3:

0ge,shi,bai,qian,wan,shiwan,bee;

always（posedgeclk_10ornegedgerst）beginif（!

rst）beginge=0;

shi=0;

bai=0;

qian=0;

wan=0;

shiwan=0;

endelsebeginif（!

tiaofen）&

（bai9）bai=bai+1;

elsebeginif（!

（qian5）beginbai=0;

qian=qian+1;

endif（!

tiaoshi）&

（wan9）wan=wan+1;

（shiwan2）beginwan=0;

shiwan=shiwan+1;

endelsebeginif（shiwan=2）&

（wan=4）beginge=0;

endif（ge9）ge=ge+1;

elsebeginge=0;

if（shi5）shi=shi+1;

elsebeginshi=0;

if（bai9）bai=bai+1;

elsebeginbai=0;

if（qian5）qian=qian+1;

elsebeginqian=0;

if（wan3）wan=wan+1;

elsebeginwan=0;

if（shiwan2）shiwan=shiwan+1;

elseshiwan=0;

endendendendendendendendendendalways（posedgeclk_10）beginif（ge=0）&

（shi=0）&

（bai=0）&

（qian=0）bee=0;

elsebee=1;

endendmodule3.3秒表模块与计时部分类似，总体思想是调整进制和提高信号频率，如下modulemiaobiao（clk_100,tm,m6,m5,m4,m3,m2,m1）;

inputtm,clk_100;

outputm6,m5,m4,m3,m2,m1;

reg3:

0m6,m5,m4,m3,m2,m1;

always（posedgeclk_100）beginif（tm）beginm6=0;

m5=0;

m4=0;

m3=0;

m2=0;

m1=0;

endelsebeginif（m19）m1=m1+1;

elsebeginm1=0;

if（m29）m2=m2+1;

elsebeginm2=0;

if（m39）m3=m3+1;

elsebeginm3=0;

if（m49）m4=m4+1;

elsebeginm4=0;

if（m59）m5=m5+1;

elsebeginm5=0;

if（m69）m6=m6+1;

elsem6=0;

endendendendendendendendmodule3.4状态机模块一般通过逻辑抽象，得出状态转换图，状态化简，状态分配，用三段式写法入下modulestate（clk1k,rst,tm,num,wela,ge,shi,bai,qian,wan,shiwan,m6,m5,m4,m3,m2,m1）;

inputclk1k,rst,tm,ge,shi,bai,qian,wan,shiwan,m6,m5,m4,m3,m2,m1;

outputnum,wela;

wire3:

0ge,shi,bai,qian,wan,shiwan,m6,m5,m4,m3,m2,m1;

0num;

reg5:

0wela;

0current_state,next_state;

parameter3:

0D1=1;

0D2=2;

0D3=3;

0D4=4;

0D5=5;

0D6=6;

0D01=7;

0D02=8;

0D03=9;

0D04=10;

0D05=11;

0D06=12;

always（posedgeclk1kornegedgerst）beginif（!

rst）current_state=D1;

elsecurrent_state=next_state;

endalways（current_state）beginif（tm=0）begincase（current_state）D1:

beginnum=m1;

wela=6b111110;

if（clk1k）next_state=D01;

elsenext_state=D1;

endD01:

beginnum=12;

wela=6b1111101;

if（clk1k）next_state=D2;

elsenext_state=D01;

endD2:

beginnum=m2;

wela=6b111101;

if（clk1k）next_state=D02;

elsenext_state=D2;

endD02:

wela=6b111011;

if（clk1k）next_state=D3;

elsenext_state=D02;

endD3:

beginnum=m3;

if（clk1k）next_state=D03;

elsenext_state=D3;

endD03:

wela=6b110111;

if（clk1k）next_state=D4;

elsenext_state=D03;

endD4:

beginnum=m4;

if（clk1k）next_state=D04;

elsenext_state=D4;

endD04:

wela=6b101111;

if（clk1k）next_state=D5;

elsenext_state=D04;

endD5:

beginnum=m5;

if（clk1k）next_state=D6;

elsenext_state=D05;

endD05:

wela=6b011111;

endD6:

beginnum=m6;

if（clk1k）next_state=D06;

elsenext_state=D6;

endD06:

if（clk1k）next_state=D1;

elsenext_state=D06;

endendcaseendelsebegincase（current_state）D1:

beginnum=ge;

beginnum=15;

beginnum=shi;

beginnum